Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27663	1			T1	329		T2	19		T4	7
auto[PWRUP]	119	1			T1	2		T48	1		T50	1
auto[ONEST_0]	62	1			T1	1		T50	1		T49	1
auto[ONEST_021]	15	1			T31	1		T157	1		T51	1
auto[ONEST_1]	65	1			T48	1		T50	1		T31	1
auto[ONEST_DONE]	3	1			T32	1		T51	1		T335	1
auto[LP_0]	128	1			T1	1		T48	3		T50	2
auto[LP_021]	39	1			T1	1		T48	1		T31	1
auto[LP_1]	139	1			T48	2		T49	1		T31	4
auto[LP_EVAL]	56	1			T1	1		T48	1		T49	2
auto[LP_SLP]	490	1			T1	17		T48	8		T50	5
auto[LP_PWRUP]	21	1			T1	1		T48	1		T31	2
auto[NP_0]	147	1			T1	2		T48	1		T49	4
auto[NP_021]	32	1			T49	1		T31	3		T37	1
auto[NP_1]	158	1			T1	2		T48	6		T50	2
auto[NP_EVAL]	37	1			T1	3		T49	2		T32	1
auto[NP_DONE]	1	1			T336	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T337

1

T51

1

T338

1

min

27198

1

T1

329

T2

19

T4

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27203	1			T1	329		T2	19		T4	7
pow[0x1]	7	1			T31	1		T157	1		T173	1
pow[0x2]	9	1			T31	1		T339	1		T340	1
pow[0x3]	37	1			T1	2		T48	1		T49	1
pow[0x4]	70	1			T48	2		T50	1		T31	1
pow[0x5]	122	1			T1	2		T49	2		T31	2
pow[0x6]	247	1			T1	5		T48	3		T50	3
pow[0x7]	500	1			T1	6		T48	7		T50	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

183

1

T1

1

T48

4

T50

3

min

26713

1

T1

310

T2

19

T4

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26713	1			T1	310		T2	19		T4	7
pow[0x4]	1	1			T37	1		-	-		-	-
pow[0x5]	1	1			T341	1		-	-		-	-
pow[0x6]	1	1			T32	1		-	-		-	-
pow[0x7]	3	1			T342	1		T343	1		T335	1
pow[0x8]	4	1			T49	1		T344	1		T345	1
pow[0x9]	11	1			T1	1		T344	1		T337	1
pow[0xa]	13	1			T48	1		T31	2		T157	1
pow[0xb]	36	1			T1	1		T50	1		T49	1
pow[0xc]	78	1			T1	2		T48	3		T50	1
pow[0xd]	129	1			T1	5		T31	6		T32	1
pow[0xe]	301	1			T1	6		T48	4		T50	1
pow[0xf]	546	1			T1	13		T48	7		T50	6