SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
97.78 | 97.78 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
adc_ctrl_hw_reset_cg_inst | 97.78 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
97.78 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 45 | 1 | 44 | 97.78 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
fsm_state_cp | 17 | 1 | 16 | 94.12 | 100 | 1 | 1 | 0 | |
lp_sample_cnt_min_max_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
lp_sample_cnt_pow_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 | |
np_sample_cnt_min_max_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
np_sample_cnt_pow_cp | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 17 | 1 | 16 | 94.12 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[NP_DONE] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[PWRDN] | 2384 | 1 | T1 | 17 | T13 | 3 | T48 | 19 | ||||
auto[PWRUP] | 133 | 1 | T48 | 2 | T49 | 2 | T31 | 1 | ||||
auto[ONEST_0] | 75 | 1 | T1 | 2 | T48 | 1 | T50 | 1 | ||||
auto[ONEST_021] | 24 | 1 | T50 | 1 | T49 | 1 | T32 | 1 | ||||
auto[ONEST_1] | 77 | 1 | T48 | 3 | T49 | 1 | T32 | 1 | ||||
auto[ONEST_DONE] | 2 | 1 | T346 | 1 | T347 | 1 | - | - | ||||
auto[LP_0] | 139 | 1 | T1 | 1 | T48 | 2 | T49 | 1 | ||||
auto[LP_021] | 36 | 1 | T49 | 1 | T27 | 1 | T32 | 2 | ||||
auto[LP_1] | 135 | 1 | T1 | 3 | T48 | 1 | T50 | 2 | ||||
auto[LP_EVAL] | 59 | 1 | T1 | 1 | T48 | 2 | T32 | 1 | ||||
auto[LP_SLP] | 505 | 1 | T1 | 6 | T48 | 2 | T50 | 6 | ||||
auto[LP_PWRUP] | 28 | 1 | T48 | 2 | T50 | 1 | T148 | 1 | ||||
auto[NP_0] | 222 | 1 | T1 | 1 | T48 | 4 | T50 | 3 | ||||
auto[NP_021] | 59 | 1 | T1 | 1 | T48 | 1 | T31 | 1 | ||||
auto[NP_1] | 234 | 1 | T1 | 4 | T48 | 2 | T50 | 1 | ||||
auto[NP_EVAL] | 33 | 1 | T27 | 1 | T157 | 1 | T173 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max | 4 | 1 | T348 | 1 | T349 | 1 | T350 | 2 | ||||
min | 1996 | 1 | T1 | 9 | T13 | 3 | T48 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
pow[0x0] | 2006 | 1 | T1 | 9 | T13 | 3 | T48 | 9 | ||||
pow[0x1] | 14 | 1 | T148 | 1 | T348 | 1 | T341 | 1 | ||||
pow[0x2] | 17 | 1 | T344 | 1 | T41 | 1 | T351 | 1 | ||||
pow[0x3] | 39 | 1 | T50 | 2 | T49 | 3 | T157 | 1 | ||||
pow[0x4] | 60 | 1 | T48 | 2 | T50 | 1 | T49 | 1 | ||||
pow[0x5] | 139 | 1 | T1 | 1 | T48 | 2 | T50 | 1 | ||||
pow[0x6] | 260 | 1 | T1 | 2 | T48 | 7 | T50 | 2 | ||||
pow[0x7] | 513 | 1 | T1 | 7 | T48 | 10 | T50 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max | 207 | 1 | T1 | 4 | T48 | 4 | T50 | 1 | ||||
min | 1451 | 1 | T1 | 1 | T13 | 3 | T48 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 16 | 0 | 16 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
pow[0x0] | 1456 | 1 | T1 | 1 | T13 | 3 | T48 | 5 | ||||
pow[0x1] | 8 | 1 | T39 | 1 | T21 | 1 | T23 | 1 | ||||
pow[0x2] | 18 | 1 | T27 | 2 | T39 | 1 | T41 | 1 | ||||
pow[0x3] | 46 | 1 | T17 | 2 | T40 | 1 | T43 | 1 | ||||
pow[0x4] | 60 | 1 | T39 | 3 | T41 | 3 | T18 | 3 | ||||
pow[0x5] | 2 | 1 | T51 | 1 | T352 | 1 | - | - | ||||
pow[0x6] | 1 | 1 | T246 | 1 | - | - | - | - | ||||
pow[0x7] | 6 | 1 | T353 | 1 | T24 | 1 | T354 | 1 | ||||
pow[0x8] | 3 | 1 | T37 | 1 | T52 | 1 | T355 | 1 | ||||
pow[0x9] | 10 | 1 | T1 | 1 | T351 | 1 | T341 | 1 | ||||
pow[0xa] | 17 | 1 | T50 | 1 | T157 | 1 | T37 | 1 | ||||
pow[0xb] | 36 | 1 | T1 | 2 | T49 | 1 | T31 | 1 | ||||
pow[0xc] | 81 | 1 | T1 | 1 | T48 | 1 | T50 | 1 | ||||
pow[0xd] | 131 | 1 | T1 | 1 | T50 | 3 | T49 | 3 | ||||
pow[0xe] | 281 | 1 | T1 | 4 | T48 | 5 | T50 | 2 | ||||
pow[0xf] | 606 | 1 | T1 | 8 | T48 | 9 | T50 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |