Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2487	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2620	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2483	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2566	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2379	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2461	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2370	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2399	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2547	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2437	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2469	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2487	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2533	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2330	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2606	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2491	0	0
adc_en_ctl_rd_A	2147483647	2272	0	0
adc_fsm_rst_rd_A	2147483647	2034	0	0
adc_intr_ctl_rd_A	2147483647	2685	0	0
adc_lp_sample_ctl_rd_A	2147483647	2120	0	0
adc_pd_ctl_rd_A	2147483647	2345	0	0
adc_sample_ctl_rd_A	2147483647	2089	0	0
adc_wakeup_ctl_rd_A	2147483647	2320	0	0
intr_enable_rd_A	2147483647	2895	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T17	153340	20	0	0
T18	0	30	0	0
T19	0	15	0	0
T20	0	5	0	0
T21	0	16	0	0
T22	0	24	0	0
T23	0	42	0	0
T24	0	39	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T17	153340	16	0	0
T18	0	24	0	0
T19	0	5	0	0
T20	0	9	0	0
T21	0	24	0	0
T22	0	16	0	0
T23	0	27	0	0
T24	0	50	0	0
T25	0	44	0	0
T26	0	11	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2483	0	0
T17	153340	17	0	0
T18	0	27	0	0
T19	0	20	0	0
T20	0	22	0	0
T21	0	19	0	0
T23	0	37	0	0
T24	0	32	0	0
T25	0	38	0	0
T26	0	8	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0
T36	0	13	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2566	0	0
T17	153340	8	0	0
T18	0	36	0	0
T19	0	16	0	0
T20	0	7	0	0
T21	0	28	0	0
T22	0	16	0	0
T23	0	49	0	0
T24	0	19	0	0
T25	0	45	0	0
T26	0	26	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2379	0	0
T17	153340	14	0	0
T18	0	21	0	0
T19	0	14	0	0
T20	0	13	0	0
T21	0	25	0	0
T22	0	11	0	0
T23	0	52	0	0
T24	0	45	0	0
T25	0	34	0	0
T26	0	7	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2461	0	0
T17	153340	8	0	0
T18	0	11	0	0
T19	0	14	0	0
T20	0	14	0	0
T21	0	9	0	0
T22	0	11	0	0
T23	0	39	0	0
T24	0	40	0	0
T25	0	32	0	0
T26	0	31	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2370	0	0
T17	153340	17	0	0
T18	0	40	0	0
T19	0	10	0	0
T20	0	10	0	0
T21	0	18	0	0
T22	0	23	0	0
T23	0	41	0	0
T24	0	34	0	0
T25	0	41	0	0
T26	0	26	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2399	0	0
T17	153340	15	0	0
T18	0	36	0	0
T19	0	17	0	0
T20	0	8	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	44	0	0
T24	0	26	0	0
T25	0	51	0	0
T26	0	15	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2547	0	0
T17	153340	14	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	11	0	0
T21	0	11	0	0
T22	0	22	0	0
T23	0	56	0	0
T24	0	34	0	0
T25	0	33	0	0
T26	0	28	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2437	0	0
T17	153340	15	0	0
T18	0	13	0	0
T19	0	17	0	0
T20	0	22	0	0
T21	0	25	0	0
T22	0	17	0	0
T23	0	57	0	0
T24	0	45	0	0
T25	0	32	0	0
T26	0	22	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2469	0	0
T17	153340	16	0	0
T18	0	24	0	0
T19	0	11	0	0
T20	0	17	0	0
T21	0	21	0	0
T22	0	18	0	0
T23	0	24	0	0
T24	0	40	0	0
T25	0	32	0	0
T26	0	30	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2487	0	0
T17	153340	19	0	0
T18	0	30	0	0
T19	0	23	0	0
T20	0	17	0	0
T21	0	7	0	0
T22	0	13	0	0
T23	0	36	0	0
T24	0	28	0	0
T25	0	43	0	0
T26	0	15	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2533	0	0
T17	153340	20	0	0
T18	0	20	0	0
T19	0	11	0	0
T20	0	17	0	0
T21	0	25	0	0
T22	0	8	0	0
T23	0	36	0	0
T24	0	32	0	0
T25	0	42	0	0
T26	0	27	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2330	0	0
T17	153340	22	0	0
T18	0	43	0	0
T19	0	14	0	0
T20	0	9	0	0
T21	0	5	0	0
T22	0	19	0	0
T23	0	34	0	0
T24	0	29	0	0
T25	0	35	0	0
T26	0	13	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T17	153340	25	0	0
T18	0	22	0	0
T19	0	6	0	0
T20	0	16	0	0
T21	0	17	0	0
T22	0	16	0	0
T23	0	28	0	0
T24	0	30	0	0
T25	0	58	0	0
T26	0	22	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2491	0	0
T17	153340	18	0	0
T18	0	33	0	0
T19	0	9	0	0
T20	0	26	0	0
T21	0	25	0	0
T22	0	12	0	0
T23	0	45	0	0
T24	0	12	0	0
T25	0	38	0	0
T26	0	22	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2272	0	0
T17	153340	25	0	0
T18	0	27	0	0
T19	0	26	0	0
T20	0	16	0	0
T21	0	12	0	0
T22	0	9	0	0
T23	0	39	0	0
T24	0	37	0	0
T25	0	45	0	0
T26	0	25	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2034	0	0
T17	153340	10	0	0
T18	0	33	0	0
T19	0	19	0	0
T20	0	16	0	0
T21	0	19	0	0
T22	0	18	0	0
T23	0	33	0	0
T24	0	56	0	0
T25	0	45	0	0
T26	0	16	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2685	0	0
T17	153340	13	0	0
T18	0	45	0	0
T19	0	18	0	0
T20	0	10	0	0
T21	0	24	0	0
T22	0	10	0	0
T23	0	51	0	0
T24	0	27	0	0
T25	0	39	0	0
T26	0	24	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120	0	0
T17	153340	12	0	0
T18	0	34	0	0
T19	0	13	0	0
T20	0	24	0	0
T21	0	32	0	0
T22	0	26	0	0
T23	0	30	0	0
T24	0	32	0	0
T25	0	35	0	0
T26	0	24	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2345	0	0
T17	153340	19	0	0
T18	0	36	0	0
T19	0	19	0	0
T20	0	10	0	0
T21	0	21	0	0
T22	0	21	0	0
T23	0	37	0	0
T24	0	28	0	0
T25	0	37	0	0
T26	0	39	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2089	0	0
T17	153340	15	0	0
T18	0	54	0	0
T19	0	30	0	0
T20	0	25	0	0
T21	0	21	0	0
T22	0	22	0	0
T23	0	26	0	0
T24	0	35	0	0
T25	0	27	0	0
T26	0	39	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2320	0	0
T17	153340	4	0	0
T18	0	39	0	0
T19	0	22	0	0
T20	0	29	0	0
T21	0	7	0	0
T22	0	13	0	0
T23	0	41	0	0
T24	0	37	0	0
T25	0	19	0	0
T26	0	18	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
T31	124766	0	0	0
T32	592843	0	0	0
T33	354327	0	0	0
T34	617884	0	0	0
T35	448959	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2895	0	0
T17	153340	63	0	0
T18	0	31	0	0
T19	0	38	0	0
T20	0	60	0	0
T21	0	28	0	0
T22	0	32	0	0
T23	0	53	0	0
T24	0	57	0	0
T27	272532	0	0	0
T28	176726	0	0	0
T29	446880	0	0	0
T30	243416	0	0	0
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T37	0	15	0	0
T38	0	22	0	0