Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1224163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1195261

1

T1

328

T4

3

T2

582

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2118203	1			T4	1		T2	942		T3	5778
values[0x0]	150396	1			T1	388		T4	6		T2	104
values[0x1]	150825	1			T1	418		T4	5		T2	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	980438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1438986

1

T1

392

T4

4

T2

684

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7003	1			T2	1		T3	19		T7	6
valid_sources[0x01]	7503	1			T3	31		T7	9		T9	8
valid_sources[0x02]	14589	1			T3	25		T7	8		T9	2
valid_sources[0x03]	11591	1			T3	25		T7	4		T9	22
valid_sources[0x04]	16152	1			T3	26		T7	13		T9	8
valid_sources[0x05]	15950	1			T3	20		T7	14		T9	15
valid_sources[0x06]	7108	1			T2	3		T3	15		T7	5
valid_sources[0x07]	6914	1			T2	5		T3	31		T7	25
valid_sources[0x08]	7336	1			T2	1		T3	19		T7	7
valid_sources[0x09]	8210	1			T3	28		T5	1		T7	8
valid_sources[0x0a]	9719	1			T2	2		T3	42		T7	5
valid_sources[0x0b]	12193	1			T2	2		T3	25		T7	8
valid_sources[0x0c]	7250	1			T3	17		T7	31		T9	16
valid_sources[0x0d]	6975	1			T3	36		T7	14		T9	21
valid_sources[0x0e]	7351	1			T2	1		T3	38		T7	13
valid_sources[0x0f]	7065	1			T2	1		T3	28		T7	15
valid_sources[0x10]	6953	1			T2	1		T3	31		T7	6
valid_sources[0x11]	8120	1			T3	19		T7	14		T9	6
valid_sources[0x12]	7348	1			T3	38		T7	14		T9	24
valid_sources[0x13]	10988	1			T2	2		T3	28		T7	6
valid_sources[0x14]	8352	1			T3	32		T7	14		T9	24
valid_sources[0x15]	6724	1			T2	1		T3	15		T7	4
valid_sources[0x16]	12197	1			T2	2		T3	23		T7	10
valid_sources[0x17]	7249	1			T2	2		T3	13		T7	22
valid_sources[0x18]	7027	1			T3	29		T7	8		T9	10
valid_sources[0x19]	7398	1			T2	4		T3	41		T7	11
valid_sources[0x1a]	9529	1			T2	3		T3	21		T7	5
valid_sources[0x1b]	15881	1			T3	11		T7	9		T9	14
valid_sources[0x1c]	11850	1			T2	1		T3	46		T7	7
valid_sources[0x1d]	12991	1			T3	24		T7	4		T9	18
valid_sources[0x1e]	7344	1			T2	2		T3	25		T7	23
valid_sources[0x1f]	12286	1			T3	23		T7	7		T9	10
valid_sources[0x20]	6866	1			T3	10		T7	10		T9	13
valid_sources[0x21]	7649	1			T3	21		T7	13		T9	11
valid_sources[0x22]	7475	1			T2	2		T3	22		T7	1
valid_sources[0x23]	7200	1			T2	1		T3	26		T7	10
valid_sources[0x24]	7479	1			T2	2		T3	13		T7	8
valid_sources[0x25]	7204	1			T2	1		T3	22		T7	8
valid_sources[0x26]	16242	1			T3	15		T7	6		T9	13
valid_sources[0x27]	11938	1			T3	15		T7	3		T9	18
valid_sources[0x28]	11650	1			T3	20		T7	13		T9	24
valid_sources[0x29]	10270	1			T3	15		T7	13		T9	9
valid_sources[0x2a]	8319	1			T2	2		T3	31		T7	15
valid_sources[0x2b]	7090	1			T3	22		T7	8		T9	10
valid_sources[0x2c]	11224	1			T3	24		T7	7		T9	13
valid_sources[0x2d]	7263	1			T3	21		T7	6		T9	22
valid_sources[0x2e]	7157	1			T2	2		T3	24		T7	12
valid_sources[0x2f]	11473	1			T3	31		T7	11		T9	26
valid_sources[0x30]	6959	1			T3	35		T7	10		T9	7
valid_sources[0x31]	8303	1			T3	23		T7	12		T9	17
valid_sources[0x32]	7411	1			T3	22		T7	4		T9	29
valid_sources[0x33]	7063	1			T3	31		T7	9		T8	1
valid_sources[0x34]	9805	1			T3	20		T7	5		T9	22
valid_sources[0x35]	18108	1			T3	42		T7	6		T9	22
valid_sources[0x36]	7107	1			T3	16		T7	4		T9	16
valid_sources[0x37]	7934	1			T3	27		T7	4		T9	12
valid_sources[0x38]	7282	1			T3	28		T7	7		T9	12
valid_sources[0x39]	7491	1			T2	5		T3	21		T7	10
valid_sources[0x3a]	8016	1			T3	32		T7	5		T9	15
valid_sources[0x3b]	11649	1			T2	1		T3	24		T7	15
valid_sources[0x3c]	11345	1			T2	1		T3	18		T7	1
valid_sources[0x3d]	12110	1			T3	19		T7	10		T8	948
valid_sources[0x3e]	10274	1			T3	30		T7	11		T9	10
valid_sources[0x3f]	20621	1			T3	29		T7	9		T9	25
valid_sources[0x40]	7530	1			T2	1		T3	23		T7	8
valid_sources[0x41]	10161	1			T2	1		T3	28		T7	17
valid_sources[0x42]	8783	1			T2	1		T3	22		T7	12
valid_sources[0x43]	25723	1			T3	30		T7	4		T9	25
valid_sources[0x44]	9779	1			T3	27		T7	10		T9	12
valid_sources[0x45]	9814	1			T3	19		T7	1		T9	12
valid_sources[0x46]	7600	1			T2	1		T3	18		T7	5
valid_sources[0x47]	7195	1			T3	25		T7	7		T9	8
valid_sources[0x48]	7208	1			T3	20		T7	5		T9	11
valid_sources[0x49]	6884	1			T3	28		T7	8		T9	16
valid_sources[0x4a]	8107	1			T3	14		T7	5		T9	13
valid_sources[0x4b]	7318	1			T2	2		T3	17		T7	3
valid_sources[0x4c]	11353	1			T2	1		T3	35		T7	8
valid_sources[0x4d]	7248	1			T3	24		T7	12		T9	18
valid_sources[0x4e]	8272	1			T1	806		T3	21		T7	6
valid_sources[0x4f]	11516	1			T2	2		T3	22		T7	2
valid_sources[0x50]	7067	1			T3	26		T7	9		T9	18
valid_sources[0x51]	7475	1			T3	29		T7	8		T9	27
valid_sources[0x52]	8138	1			T2	2		T3	27		T7	7
valid_sources[0x53]	11763	1			T3	29		T7	6		T9	15
valid_sources[0x54]	7067	1			T3	22		T7	10		T9	14
valid_sources[0x55]	7261	1			T2	1		T3	18		T7	6
valid_sources[0x56]	6994	1			T3	14		T7	4		T9	19
valid_sources[0x57]	7071	1			T2	1		T3	27		T7	5
valid_sources[0x58]	16261	1			T2	2		T3	17		T7	8
valid_sources[0x59]	8531	1			T2	1		T3	19		T7	4
valid_sources[0x5a]	7252	1			T2	1		T3	18		T7	23
valid_sources[0x5b]	25316	1			T3	28		T7	4		T9	14
valid_sources[0x5c]	9308	1			T3	26		T7	4		T9	8
valid_sources[0x5d]	7779	1			T2	2		T3	29		T7	13
valid_sources[0x5e]	9110	1			T2	2		T3	15		T7	13
valid_sources[0x5f]	8096	1			T2	946		T3	26		T7	7
valid_sources[0x60]	7035	1			T2	3		T3	15		T7	9
valid_sources[0x61]	10123	1			T2	1		T3	30		T7	9
valid_sources[0x62]	6865	1			T3	36		T7	12		T9	27
valid_sources[0x63]	8664	1			T2	1		T3	34		T7	4
valid_sources[0x64]	8377	1			T3	42		T7	6		T9	5
valid_sources[0x65]	7020	1			T2	1		T3	22		T7	10
valid_sources[0x66]	11363	1			T2	4		T3	19		T7	6
valid_sources[0x67]	10244	1			T2	2		T3	21		T9	25
valid_sources[0x68]	21904	1			T2	1		T3	41		T6	13113
valid_sources[0x69]	7197	1			T2	2		T3	25		T7	5
valid_sources[0x6a]	8306	1			T3	16		T7	7		T9	15
valid_sources[0x6b]	6702	1			T2	1		T3	18		T7	8
valid_sources[0x6c]	7538	1			T2	1		T3	21		T7	11
valid_sources[0x6d]	12060	1			T3	20		T7	3		T9	14
valid_sources[0x6e]	7112	1			T2	2		T3	39		T7	10
valid_sources[0x6f]	6845	1			T2	1		T3	21		T7	1
valid_sources[0x70]	7408	1			T2	1		T3	22		T7	14
valid_sources[0x71]	7172	1			T2	2		T3	11		T7	9
valid_sources[0x72]	9978	1			T3	38		T7	5		T9	22
valid_sources[0x73]	12543	1			T2	3		T3	30		T7	5
valid_sources[0x74]	8993	1			T3	21		T7	14		T9	17
valid_sources[0x75]	8237	1			T2	1		T3	39		T7	13
valid_sources[0x76]	7648	1			T2	2		T3	28		T7	8
valid_sources[0x77]	8488	1			T2	2		T3	16		T7	10
valid_sources[0x78]	9941	1			T2	2		T3	41		T7	7
valid_sources[0x79]	9128	1			T2	1		T3	33		T7	6
valid_sources[0x7a]	11953	1			T3	13		T7	9		T9	10
valid_sources[0x7b]	7075	1			T3	17		T7	12		T9	23
valid_sources[0x7c]	12524	1			T3	26		T7	5		T9	23
valid_sources[0x7d]	7463	1			T3	24		T7	12		T9	15
valid_sources[0x7e]	11813	1			T3	26		T7	3		T9	15
valid_sources[0x7f]	7727	1			T3	25		T7	11		T9	8
valid_sources[0x80]	7808	1			T2	2		T3	9		T7	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1054884

1

T4

1

T2

500

T3

2906

values[0x0]

all_enables

biggest_size

81528

1

T1

193

T4

2

T2

46

values[0x1]

all_enables

biggest_size

58849

1

T1

135

T2

36

T3

79