Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29350	1			T1	209		T2	5		T3	19
auto[PWRUP]	96	1			T1	2		T14	1		T26	2
auto[ONEST_0]	95	1			T7	1		T26	1		T41	1
auto[ONEST_021]	14	1			T217	1		T218	1		T22	1
auto[ONEST_1]	69	1			T1	1		T13	1		T26	1
auto[ONEST_DONE]	6	1			T185	1		T42	1		T219	1
auto[LP_0]	119	1			T1	1		T13	2		T14	1
auto[LP_021]	20	1			T7	1		T26	1		T41	1
auto[LP_1]	127	1			T7	1		T14	1		T26	4
auto[LP_EVAL]	73	1			T7	1		T13	1		T26	2
auto[LP_SLP]	506	1			T1	5		T7	3		T14	1
auto[LP_PWRUP]	28	1			T13	1		T41	1		T220	1
auto[NP_0]	179	1			T1	3		T13	2		T14	1
auto[NP_021]	31	1			T164	1		T220	1		T221	1
auto[NP_1]	151	1			T1	3		T7	2		T14	1
auto[NP_EVAL]	33	1			T7	1		T185	1		T222	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T218

1

T223

1

T224

1

min

28763

1

T1

199

T2

5

T3

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28774	1			T1	199		T2	5		T3	19
pow[0x1]	12	1			T160	1		T43	2		T225	2
pow[0x2]	21	1			T226	1		T227	2		T19	1
pow[0x3]	33	1			T26	1		T164	1		T193	1
pow[0x4]	62	1			T26	3		T41	1		T185	1
pow[0x5]	124	1			T1	3		T13	1		T26	1
pow[0x6]	292	1			T1	3		T7	1		T13	2
pow[0x7]	510	1			T1	3		T7	6		T13	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

205

1

T1

6

T7

2

T26

2

min

28308

1

T1

198

T2

5

T3

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28308	1			T1	198		T2	5		T3	19
pow[0x5]	3	1			T225	1		T228	1		T229	1
pow[0x6]	3	1			T225	1		T230	1		T231	1
pow[0x7]	3	1			T232	1		T233	1		T234	1
pow[0x8]	7	1			T164	1		T43	1		T235	1
pow[0x9]	9	1			T41	1		T236	1		T19	1
pow[0xa]	15	1			T164	1		T236	2		T227	1
pow[0xb]	46	1			T164	1		T220	1		T221	2
pow[0xc]	73	1			T14	1		T185	1		T164	2
pow[0xd]	150	1			T13	1		T26	2		T185	1
pow[0xe]	300	1			T1	2		T13	1		T26	4
pow[0xf]	575	1			T1	5		T7	5		T13	4