Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2376	1			T1	12		T2	4		T3	3
auto[PWRUP]	143	1			T1	2		T7	1		T26	3
auto[ONEST_0]	75	1			T1	1		T7	1		T14	2
auto[ONEST_021]	16	1			T7	1		T13	1		T41	1
auto[ONEST_1]	97	1			T26	2		T164	1		T217	4
auto[ONEST_DONE]	3	1			T227	1		T225	1		T265	1
auto[LP_0]	126	1			T7	2		T33	1		T13	3
auto[LP_021]	35	1			T13	1		T41	1		T222	1
auto[LP_1]	131	1			T1	2		T7	1		T33	1
auto[LP_EVAL]	62	1			T1	1		T7	1		T14	1
auto[LP_SLP]	567	1			T1	4		T7	6		T13	3
auto[LP_PWRUP]	38	1			T27	1		T217	1		T220	1
auto[NP_0]	218	1			T1	4		T7	1		T13	3
auto[NP_021]	56	1			T7	4		T33	1		T26	1
auto[NP_1]	232	1			T1	1		T7	2		T33	1
auto[NP_EVAL]	39	1			T33	2		T26	2		T220	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T1

1

T232

1

T227

1

min

2068

1

T1

4

T2

4

T3

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2091	1			T1	4		T2	4		T3	3
pow[0x1]	11	1			T221	1		T188	1		T307	1
pow[0x2]	19	1			T1	1		T217	1		T160	1
pow[0x3]	42	1			T13	2		T41	1		T185	1
pow[0x4]	78	1			T1	2		T7	2		T26	4
pow[0x5]	130	1			T7	2		T13	2		T14	1
pow[0x6]	258	1			T1	3		T7	3		T13	3
pow[0x7]	556	1			T1	5		T7	5		T13	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T1

5

T7

3

T13

1

min

1458

1

T1

2

T2

4

T3

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1464	1			T1	2		T2	4		T3	3
pow[0x1]	8	1			T362	1		T363	4		T364	1
pow[0x2]	22	1			T16	2		T17	2		T124	3
pow[0x3]	35	1			T7	3		T16	1		T91	2
pow[0x4]	68	1			T7	1		T33	4		T14	2
pow[0x6]	1	1			T365	1		-	-		-	-
pow[0x8]	6	1			T22	1		T235	1		T230	1
pow[0x9]	6	1			T221	2		T188	1		T366	1
pow[0xa]	24	1			T164	3		T16	1		T220	1
pow[0xb]	35	1			T232	1		T160	1		T188	1
pow[0xc]	79	1			T7	1		T13	3		T41	1
pow[0xd]	146	1			T1	2		T7	2		T13	1
pow[0xe]	304	1			T1	2		T7	3		T13	4
pow[0xf]	623	1			T1	6		T7	7		T13	4