Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2462	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2218	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2298	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2474	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2362	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2359	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2312	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2410	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2380	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2466	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2430	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2412	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2525	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2353	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2249	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2569	0	0
adc_en_ctl_rd_A	2147483647	2049	0	0
adc_fsm_rst_rd_A	2147483647	1729	0	0
adc_intr_ctl_rd_A	2147483647	2516	0	0
adc_lp_sample_ctl_rd_A	2147483647	1630	0	0
adc_pd_ctl_rd_A	2147483647	2192	0	0
adc_sample_ctl_rd_A	2147483647	1665	0	0
adc_wakeup_ctl_rd_A	2147483647	1789	0	0
intr_enable_rd_A	2147483647	2354	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2462	0	0
T13	718700	22	0	0
T14	931711	35	0	0
T15	0	11	0	0
T16	0	49	0	0
T17	0	46	0	0
T18	0	37	0	0
T19	0	18	0	0
T20	0	26	0	0
T21	0	16	0	0
T22	0	27	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2218	0	0
T13	718700	15	0	0
T14	931711	37	0	0
T15	0	3	0	0
T16	0	46	0	0
T17	0	53	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	0	27	0	0
T21	0	19	0	0
T22	0	15	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2298	0	0
T13	718700	13	0	0
T14	931711	25	0	0
T15	0	10	0	0
T16	0	37	0	0
T17	0	44	0	0
T18	0	46	0	0
T19	0	13	0	0
T20	0	24	0	0
T21	0	18	0	0
T22	0	26	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T13	718700	18	0	0
T14	931711	24	0	0
T16	0	54	0	0
T17	0	34	0	0
T18	0	37	0	0
T19	0	11	0	0
T20	0	31	0	0
T21	0	11	0	0
T22	0	25	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0
T31	0	12	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2362	0	0
T13	718700	18	0	0
T14	931711	25	0	0
T15	0	5	0	0
T16	0	42	0	0
T17	0	48	0	0
T18	0	39	0	0
T19	0	12	0	0
T20	0	18	0	0
T21	0	25	0	0
T22	0	19	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2359	0	0
T13	718700	15	0	0
T14	931711	35	0	0
T15	0	5	0	0
T16	0	36	0	0
T17	0	42	0	0
T18	0	44	0	0
T19	0	47	0	0
T20	0	14	0	0
T21	0	34	0	0
T22	0	10	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2312	0	0
T13	718700	11	0	0
T14	931711	30	0	0
T15	0	4	0	0
T16	0	29	0	0
T17	0	37	0	0
T18	0	50	0	0
T19	0	40	0	0
T20	0	15	0	0
T21	0	13	0	0
T22	0	12	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T13	718700	24	0	0
T14	931711	49	0	0
T15	0	6	0	0
T16	0	47	0	0
T17	0	35	0	0
T18	0	36	0	0
T19	0	16	0	0
T20	0	37	0	0
T21	0	36	0	0
T22	0	29	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2380	0	0
T13	718700	20	0	0
T14	931711	33	0	0
T15	0	7	0	0
T16	0	23	0	0
T17	0	41	0	0
T18	0	44	0	0
T19	0	16	0	0
T20	0	15	0	0
T21	0	23	0	0
T22	0	21	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2466	0	0
T13	718700	13	0	0
T14	931711	26	0	0
T15	0	1	0	0
T16	0	23	0	0
T17	0	40	0	0
T18	0	32	0	0
T19	0	30	0	0
T20	0	9	0	0
T21	0	21	0	0
T22	0	17	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2430	0	0
T13	718700	24	0	0
T14	931711	32	0	0
T15	0	19	0	0
T16	0	39	0	0
T17	0	51	0	0
T18	0	44	0	0
T19	0	28	0	0
T20	0	21	0	0
T21	0	18	0	0
T22	0	17	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2412	0	0
T13	718700	18	0	0
T14	931711	32	0	0
T15	0	9	0	0
T16	0	31	0	0
T17	0	37	0	0
T18	0	38	0	0
T19	0	19	0	0
T20	0	29	0	0
T21	0	14	0	0
T22	0	14	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2525	0	0
T13	718700	15	0	0
T14	931711	26	0	0
T16	0	37	0	0
T17	0	51	0	0
T18	0	32	0	0
T19	0	16	0	0
T20	0	21	0	0
T21	0	12	0	0
T22	0	30	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0
T31	0	13	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2353	0	0
T13	718700	25	0	0
T14	931711	53	0	0
T15	0	4	0	0
T16	0	36	0	0
T17	0	51	0	0
T18	0	29	0	0
T19	0	14	0	0
T20	0	27	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2249	0	0
T13	718700	16	0	0
T14	931711	45	0	0
T16	0	43	0	0
T17	0	38	0	0
T18	0	38	0	0
T19	0	20	0	0
T20	0	8	0	0
T21	0	20	0	0
T22	0	12	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0
T31	0	30	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T13	718700	23	0	0
T14	931711	54	0	0
T15	0	17	0	0
T16	0	51	0	0
T17	0	44	0	0
T18	0	52	0	0
T19	0	23	0	0
T20	0	8	0	0
T21	0	16	0	0
T22	0	18	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2049	0	0
T13	718700	6	0	0
T14	931711	31	0	0
T15	0	2	0	0
T16	0	42	0	0
T17	0	37	0	0
T18	0	44	0	0
T19	0	1	0	0
T20	0	13	0	0
T21	0	16	0	0
T22	0	19	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1729	0	0
T13	718700	13	0	0
T14	931711	20	0	0
T15	0	7	0	0
T16	0	36	0	0
T17	0	25	0	0
T18	0	43	0	0
T19	0	10	0	0
T20	0	23	0	0
T21	0	17	0	0
T22	0	12	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T13	718700	17	0	0
T14	931711	30	0	0
T15	0	4	0	0
T16	0	35	0	0
T17	0	55	0	0
T18	0	53	0	0
T19	0	28	0	0
T20	0	18	0	0
T21	0	22	0	0
T22	0	15	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1630	0	0
T13	718700	17	0	0
T14	931711	29	0	0
T15	0	10	0	0
T16	0	30	0	0
T17	0	56	0	0
T18	0	41	0	0
T19	0	30	0	0
T20	0	18	0	0
T21	0	19	0	0
T22	0	15	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T13	718700	22	0	0
T14	931711	30	0	0
T15	0	10	0	0
T16	0	40	0	0
T17	0	28	0	0
T18	0	39	0	0
T19	0	16	0	0
T20	0	28	0	0
T21	0	27	0	0
T22	0	9	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1665	0	0
T13	718700	15	0	0
T14	931711	17	0	0
T15	0	23	0	0
T16	0	32	0	0
T17	0	50	0	0
T18	0	24	0	0
T19	0	28	0	0
T20	0	22	0	0
T21	0	13	0	0
T22	0	10	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T13	718700	22	0	0
T14	931711	18	0	0
T15	0	16	0	0
T16	0	40	0	0
T17	0	42	0	0
T18	0	37	0	0
T19	0	34	0	0
T20	0	11	0	0
T21	0	23	0	0
T22	0	18	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	0	0	0
T30	321023	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2354	0	0
T13	718700	37	0	0
T14	931711	55	0	0
T15	0	18	0	0
T16	0	91	0	0
T17	0	35	0	0
T18	0	67	0	0
T19	0	31	0	0
T20	0	32	0	0
T23	704223	0	0	0
T24	792577	0	0	0
T25	25417	0	0	0
T26	577404	0	0	0
T27	780509	0	0	0
T28	787888	0	0	0
T29	168301	26	0	0
T30	321023	0	0	0
T32	0	10	0	0