Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1212200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1188157

1

T1

987

T2

971

T3

477

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2106460	1			T1	1680		T2	1699		T3	853
values[0x0]	146285	1			T1	98		T2	101		T3	55
values[0x1]	147612	1			T1	89		T2	110		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	971009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1429348

1

T1

1185

T2

1174

T3

581

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7858	1			T1	3		T2	4		T4	5
valid_sources[0x01]	9756	1			T1	3		T2	3		T4	1
valid_sources[0x02]	8205	1			T1	10		T2	2		T4	2
valid_sources[0x03]	7161	1			T2	2		T4	2		T7	19
valid_sources[0x04]	7447	1			T1	2		T2	1		T4	1
valid_sources[0x05]	11488	1			T1	1		T2	2		T7	16
valid_sources[0x06]	7217	1			T1	3		T2	1		T7	42
valid_sources[0x07]	6843	1			T1	4		T2	5		T4	2
valid_sources[0x08]	7895	1			T1	5		T2	1		T4	2
valid_sources[0x09]	12528	1			T1	7		T2	976		T7	17
valid_sources[0x0a]	7973	1			T1	7		T2	3		T4	1
valid_sources[0x0b]	6748	1			T1	2		T2	5		T4	2
valid_sources[0x0c]	8998	1			T1	2		T2	5		T4	15
valid_sources[0x0d]	11136	1			T1	7		T2	3		T4	3
valid_sources[0x0e]	7021	1			T1	1		T2	5		T4	3
valid_sources[0x0f]	11285	1			T2	4		T4	5		T5	3
valid_sources[0x10]	7205	1			T1	3		T2	1		T4	3
valid_sources[0x11]	9959	1			T1	4		T2	8		T4	2
valid_sources[0x12]	7299	1			T1	2		T2	4		T4	8
valid_sources[0x13]	11097	1			T1	1		T2	6		T4	1
valid_sources[0x14]	9943	1			T1	3		T2	6		T4	5
valid_sources[0x15]	9815	1			T1	1		T2	3		T4	9
valid_sources[0x16]	7037	1			T1	11		T2	1		T4	2
valid_sources[0x17]	11590	1			T1	2		T2	3		T4	8
valid_sources[0x18]	7340	1			T1	3		T2	5		T4	3
valid_sources[0x19]	7041	1			T1	3		T2	2		T4	2
valid_sources[0x1a]	7047	1			T1	10		T2	3		T4	5
valid_sources[0x1b]	7037	1			T1	9		T2	2		T4	10
valid_sources[0x1c]	10601	1			T1	3		T4	7		T7	19
valid_sources[0x1d]	7299	1			T1	3		T2	10		T4	2
valid_sources[0x1e]	7365	1			T1	7		T2	1		T4	1
valid_sources[0x1f]	6646	1			T1	4		T2	4		T4	7
valid_sources[0x20]	8192	1			T1	6		T2	1		T4	4
valid_sources[0x21]	7426	1			T1	3		T2	5		T4	3
valid_sources[0x22]	11793	1			T1	5		T2	2		T4	6
valid_sources[0x23]	9498	1			T1	8		T2	2		T7	10
valid_sources[0x24]	8974	1			T1	1		T2	2		T4	3
valid_sources[0x25]	7049	1			T1	1		T2	1		T4	1
valid_sources[0x26]	7044	1			T1	1		T2	2		T4	3
valid_sources[0x27]	8055	1			T1	6		T2	3		T4	1
valid_sources[0x28]	9571	1			T1	2		T2	2		T6	3
valid_sources[0x29]	7033	1			T1	1		T2	5		T4	3
valid_sources[0x2a]	15997	1			T1	3		T2	3		T7	20
valid_sources[0x2b]	12353	1			T1	2		T2	4		T4	18
valid_sources[0x2c]	7226	1			T1	5		T2	3		T4	5
valid_sources[0x2d]	8152	1			T2	3		T4	5		T5	1
valid_sources[0x2e]	7977	1			T2	2		T4	4		T7	24
valid_sources[0x2f]	7406	1			T1	1		T2	2		T4	2
valid_sources[0x30]	10018	1			T1	3		T2	7		T4	5
valid_sources[0x31]	8540	1			T1	2		T2	4		T4	2
valid_sources[0x32]	11740	1			T1	2		T2	2		T7	10
valid_sources[0x33]	7908	1			T1	6		T2	2		T4	6
valid_sources[0x34]	7852	1			T1	4		T2	3		T5	2
valid_sources[0x35]	6519	1			T2	8		T4	1		T7	35
valid_sources[0x36]	20120	1			T1	6		T2	5		T4	3
valid_sources[0x37]	7325	1			T1	3		T2	1		T4	4
valid_sources[0x38]	11227	1			T1	3		T2	3		T4	10
valid_sources[0x39]	11202	1			T1	6		T2	5		T4	1
valid_sources[0x3a]	6861	1			T1	14		T2	10		T4	5
valid_sources[0x3b]	7413	1			T1	7		T2	4		T4	7
valid_sources[0x3c]	7086	1			T1	5		T2	6		T4	9
valid_sources[0x3d]	7166	1			T1	7		T2	6		T7	17
valid_sources[0x3e]	13611	1			T1	1		T2	1		T4	3
valid_sources[0x3f]	12983	1			T1	2		T2	3		T4	1
valid_sources[0x40]	6987	1			T1	1		T2	1		T4	5
valid_sources[0x41]	6946	1			T1	5		T2	1		T4	5
valid_sources[0x42]	10099	1			T1	2		T2	7		T7	15
valid_sources[0x43]	10229	1			T1	5		T4	3		T7	11
valid_sources[0x44]	11190	1			T1	3		T2	6		T7	28
valid_sources[0x45]	12492	1			T1	2		T2	5		T4	7
valid_sources[0x46]	8073	1			T1	1		T2	5		T4	4
valid_sources[0x47]	7510	1			T4	1		T7	23		T9	1
valid_sources[0x48]	11738	1			T1	9		T2	3		T4	3
valid_sources[0x49]	7294	1			T1	4		T2	2		T4	7
valid_sources[0x4a]	8571	1			T1	9		T2	6		T4	1
valid_sources[0x4b]	7215	1			T1	3		T2	1		T4	9
valid_sources[0x4c]	6726	1			T1	6		T2	4		T4	1
valid_sources[0x4d]	7908	1			T1	5		T2	6		T4	4
valid_sources[0x4e]	7028	1			T2	8		T4	2		T7	25
valid_sources[0x4f]	10134	1			T1	1		T2	2		T4	2
valid_sources[0x50]	7978	1			T1	2		T2	2		T4	5
valid_sources[0x51]	11926	1			T1	1		T2	4		T4	5
valid_sources[0x52]	7140	1			T1	3		T2	5		T4	3
valid_sources[0x53]	6985	1			T1	5		T4	2		T7	41
valid_sources[0x54]	14158	1			T1	6		T2	8		T4	3
valid_sources[0x55]	7102	1			T1	4		T2	7		T4	6
valid_sources[0x56]	6931	1			T1	1		T2	6		T4	3
valid_sources[0x57]	6966	1			T1	1		T2	2		T4	3
valid_sources[0x58]	7295	1			T1	2		T2	3		T4	16
valid_sources[0x59]	9933	1			T1	2		T2	3		T4	1
valid_sources[0x5a]	7140	1			T1	3		T2	3		T7	25
valid_sources[0x5b]	13680	1			T1	1		T2	2		T4	14
valid_sources[0x5c]	13688	1			T1	3		T2	2		T4	3
valid_sources[0x5d]	11549	1			T1	1		T2	3		T4	1
valid_sources[0x5e]	11259	1			T1	4		T2	3		T4	2
valid_sources[0x5f]	6979	1			T1	8		T2	4		T4	6
valid_sources[0x60]	19644	1			T1	4		T2	7		T4	4
valid_sources[0x61]	7614	1			T1	4		T2	1		T7	17
valid_sources[0x62]	11102	1			T1	2		T2	2		T4	3
valid_sources[0x63]	7073	1			T1	4		T2	6		T4	4
valid_sources[0x64]	12324	1			T1	2		T2	4		T4	7
valid_sources[0x65]	7042	1			T1	5		T2	4		T4	1
valid_sources[0x66]	7035	1			T1	2		T2	6		T4	1
valid_sources[0x67]	13065	1			T1	5		T2	3		T4	3
valid_sources[0x68]	11223	1			T1	8		T2	3		T6	31
valid_sources[0x69]	12398	1			T1	2		T2	2		T4	1
valid_sources[0x6a]	15259	1			T1	5		T2	12		T4	3
valid_sources[0x6b]	11296	1			T1	3		T4	2		T7	40
valid_sources[0x6c]	9606	1			T1	5		T2	3		T4	7
valid_sources[0x6d]	8392	1			T1	5		T2	6		T4	4
valid_sources[0x6e]	11190	1			T1	1		T2	2		T4	1
valid_sources[0x6f]	7245	1			T1	2		T2	6		T4	2
valid_sources[0x70]	7383	1			T1	2		T2	2		T6	5
valid_sources[0x71]	20735	1			T1	3		T2	5		T4	10
valid_sources[0x72]	11895	1			T1	2		T2	2		T4	2
valid_sources[0x73]	9914	1			T1	7		T2	2		T4	6
valid_sources[0x74]	7627	1			T1	1		T2	1		T7	17
valid_sources[0x75]	15301	1			T2	6		T6	2		T7	9
valid_sources[0x76]	11142	1			T1	7		T2	2		T4	1
valid_sources[0x77]	7800	1			T1	1		T2	2		T4	1
valid_sources[0x78]	9114	1			T1	5		T2	4		T4	1
valid_sources[0x79]	11608	1			T1	3		T2	6		T4	8
valid_sources[0x7a]	7407	1			T1	4		T2	6		T4	7
valid_sources[0x7b]	6876	1			T1	4		T2	3		T4	5
valid_sources[0x7c]	9998	1			T1	3		T2	5		T7	16
valid_sources[0x7d]	7749	1			T1	1		T2	3		T3	964
valid_sources[0x7e]	7753	1			T1	2		T2	4		T4	3
valid_sources[0x7f]	8933	1			T1	4		T2	3		T7	20
valid_sources[0x80]	6804	1			T1	4		T2	2		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049946

1

T1

888

T2

873

T3

425

values[0x0]

all_enables

biggest_size

80018

1

T1

63

T2

54

T3

33

values[0x1]

all_enables

biggest_size

58193

1

T1

36

T2

44

T3

19