Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29112	1			T1	15		T2	10		T3	6
auto[PWRUP]	105	1			T40	3		T41	2		T90	1
auto[ONEST_0]	68	1			T27	1		T40	1		T41	1
auto[ONEST_021]	25	1			T27	1		T16	1		T185	1
auto[ONEST_1]	66	1			T27	2		T42	1		T186	1
auto[ONEST_DONE]	1	1			T187	1		-	-		-	-
auto[LP_0]	113	1			T27	2		T40	2		T41	1
auto[LP_021]	27	1			T40	1		T17	1		T188	1
auto[LP_1]	146	1			T27	2		T40	1		T41	1
auto[LP_EVAL]	57	1			T41	3		T42	1		T16	1
auto[LP_SLP]	500	1			T27	11		T40	13		T41	9
auto[LP_PWRUP]	24	1			T40	1		T42	1		T189	1
auto[NP_0]	163	1			T27	3		T33	1		T40	2
auto[NP_021]	33	1			T40	1		T41	1		T186	2
auto[NP_1]	160	1			T27	2		T33	1		T40	6
auto[NP_EVAL]	32	1			T190	1		T191	1		T192	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T27

1

T193

1

T194

1

min

28627

1

T1

15

T2

10

T3

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28636	1			T1	15		T2	10		T3	6
pow[0x1]	8	1			T17	1		T195	1		T196	1
pow[0x2]	15	1			T191	2		T197	1		T198	3
pow[0x3]	31	1			T27	1		T42	1		T190	1
pow[0x4]	60	1			T27	1		T40	1		T42	1
pow[0x5]	121	1			T27	2		T40	5		T41	5
pow[0x6]	273	1			T27	1		T33	1		T40	5
pow[0x7]	499	1			T27	7		T33	1		T40	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

195

1

T27

7

T40

3

T41

2

min

28152

1

T1

15

T2

10

T3

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28152	1			T1	15		T2	10		T3	6
pow[0x5]	2	1			T42	1		T199	1		-	-
pow[0x7]	2	1			T192	1		T200	1		-	-
pow[0x8]	4	1			T201	1		T202	1		T203	1
pow[0x9]	9	1			T90	1		T204	1		T205	1
pow[0xa]	26	1			T186	1		T185	1		T17	1
pow[0xb]	48	1			T190	1		T186	1		T185	2
pow[0xc]	75	1			T27	1		T40	2		T41	1
pow[0xd]	138	1			T40	6		T41	1		T90	3
pow[0xe]	261	1			T27	11		T40	3		T41	1
pow[0xf]	544	1			T27	8		T33	1		T40	8