Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2292	1			T6	3		T9	12		T13	8
auto[PWRUP]	122	1			T9	1		T27	1		T40	2
auto[ONEST_0]	63	1			T27	1		T41	1		T90	1
auto[ONEST_021]	10	1			T41	2		T37	1		T188	1
auto[ONEST_1]	75	1			T27	1		T40	1		T34	1
auto[ONEST_DONE]	5	1			T186	1		T192	1		T206	1
auto[LP_0]	117	1			T27	1		T40	3		T41	1
auto[LP_021]	29	1			T42	1		T192	2		T185	1
auto[LP_1]	147	1			T27	3		T40	2		T41	1
auto[LP_EVAL]	58	1			T27	1		T33	1		T42	1
auto[LP_SLP]	519	1			T13	1		T27	6		T33	1
auto[LP_PWRUP]	32	1			T27	1		T41	1		T42	2
auto[NP_0]	223	1			T9	2		T13	3		T27	6
auto[NP_021]	55	1			T9	2		T40	2		T34	1
auto[NP_1]	213	1			T27	3		T33	1		T40	1
auto[NP_EVAL]	32	1			T40	1		T34	1		T190	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T186

1

T189

1

T207

1

min

1909

1

T6

3

T9

16

T13

12

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1918	1			T6	3		T9	16		T13	12
pow[0x1]	14	1			T34	1		T42	1		T190	1
pow[0x2]	17	1			T9	1		T27	1		T16	1
pow[0x3]	38	1			T27	2		T40	1		T41	1
pow[0x4]	55	1			T27	1		T33	2		T40	1
pow[0x5]	133	1			T40	1		T90	1		T42	8
pow[0x6]	271	1			T27	3		T40	3		T41	3
pow[0x7]	522	1			T27	11		T40	10		T41	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

192

1

T27

1

T33

1

T40

4

min

1323

1

T6

3

T9

13

T13

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1328	1			T6	3		T9	13		T13	9
pow[0x1]	13	1			T34	1		T36	2		T19	1
pow[0x2]	16	1			T14	1		T34	2		T37	1
pow[0x3]	56	1			T13	1		T33	1		T34	1
pow[0x4]	61	1			T9	3		T13	2		T14	3
pow[0x8]	3	1			T192	1		T208	1		T209	1
pow[0x9]	7	1			T210	1		T208	1		T211	1
pow[0xa]	21	1			T186	1		T195	1		T207	1
pow[0xb]	38	1			T27	2		T42	1		T192	1
pow[0xc]	78	1			T27	3		T40	2		T41	2
pow[0xd]	152	1			T27	1		T40	2		T42	4
pow[0xe]	280	1			T27	2		T40	3		T41	5
pow[0xf]	602	1			T9	1		T27	8		T33	2