Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1203883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176620

1

T1

901

T2

14

T3

54

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2084258	1			T1	1670		T3	81		T4	81
values[0x0]	147272	1			T1	102		T2	12		T3	31
values[0x1]	148973	1			T1	85		T2	19		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	964813	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415690

1

T1

1080

T2

17

T3

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10618	1			T5	12		T6	10		T9	11
valid_sources[0x01]	8501	1			T1	4		T2	2		T5	23
valid_sources[0x02]	6696	1			T5	26		T6	12		T8	1
valid_sources[0x03]	8928	1			T1	4		T5	20		T6	5
valid_sources[0x04]	6596	1			T5	46		T6	18		T9	5
valid_sources[0x05]	6906	1			T1	8		T5	4		T6	25
valid_sources[0x06]	11809	1			T5	17		T6	53		T9	11
valid_sources[0x07]	7563	1			T5	9		T6	35		T9	4
valid_sources[0x08]	7377	1			T1	8		T5	21		T6	7
valid_sources[0x09]	10198	1			T5	2		T6	27		T9	6
valid_sources[0x0a]	7306	1			T1	5		T5	16		T6	10
valid_sources[0x0b]	10994	1			T1	7		T5	4		T6	19
valid_sources[0x0c]	15421	1			T1	9		T5	14		T6	17
valid_sources[0x0d]	7097	1			T1	12		T5	12		T6	5
valid_sources[0x0e]	17833	1			T1	2		T5	17		T6	7
valid_sources[0x0f]	7030	1			T1	5		T6	8		T10	11
valid_sources[0x10]	7097	1			T1	5		T5	30		T6	23
valid_sources[0x11]	6952	1			T1	2		T5	20		T6	15
valid_sources[0x12]	7245	1			T1	2		T5	6		T6	30
valid_sources[0x13]	7874	1			T1	1		T5	26		T6	22
valid_sources[0x14]	11257	1			T1	11		T5	3		T6	27
valid_sources[0x15]	12866	1			T1	9		T5	8		T6	14
valid_sources[0x16]	8026	1			T1	1		T5	16		T6	20
valid_sources[0x17]	8042	1			T5	18		T6	13		T10	6
valid_sources[0x18]	8135	1			T1	4		T5	19		T6	19
valid_sources[0x19]	8206	1			T5	12		T6	14		T10	5
valid_sources[0x1a]	6718	1			T1	5		T5	15		T6	32
valid_sources[0x1b]	19790	1			T1	4		T5	27		T6	10
valid_sources[0x1c]	11375	1			T5	5		T6	18		T7	4
valid_sources[0x1d]	9485	1			T5	23		T6	11		T10	23
valid_sources[0x1e]	7078	1			T3	144		T5	4		T6	18
valid_sources[0x1f]	7207	1			T1	5		T2	3		T5	16
valid_sources[0x20]	7369	1			T1	9		T5	23		T6	12
valid_sources[0x21]	6926	1			T5	15		T6	11		T9	2
valid_sources[0x22]	9619	1			T1	4		T5	14		T6	6
valid_sources[0x23]	7576	1			T1	7		T5	8		T6	40
valid_sources[0x24]	8341	1			T5	20		T6	32		T9	8
valid_sources[0x25]	7007	1			T1	1		T5	6		T6	37
valid_sources[0x26]	11206	1			T1	10		T5	40		T6	14
valid_sources[0x27]	11428	1			T5	12		T6	4		T10	12
valid_sources[0x28]	15678	1			T1	7		T5	21		T6	24
valid_sources[0x29]	9746	1			T1	3		T5	1		T6	41
valid_sources[0x2a]	19891	1			T1	9		T5	19		T6	5
valid_sources[0x2b]	11589	1			T1	2		T5	11		T6	10
valid_sources[0x2c]	7015	1			T1	6		T2	1		T5	33
valid_sources[0x2d]	8132	1			T1	7		T5	15		T6	20
valid_sources[0x2e]	10420	1			T1	1		T5	6		T6	8
valid_sources[0x2f]	7914	1			T5	20		T6	8		T9	11
valid_sources[0x30]	11959	1			T1	2		T5	4		T6	28
valid_sources[0x31]	10289	1			T1	2		T5	17		T6	22
valid_sources[0x32]	15972	1			T1	16		T5	5		T6	35
valid_sources[0x33]	7873	1			T1	5		T5	12		T6	1
valid_sources[0x34]	6899	1			T5	13		T6	18		T9	16
valid_sources[0x35]	7304	1			T1	2		T5	13		T6	22
valid_sources[0x36]	14484	1			T1	1		T5	24		T6	10
valid_sources[0x37]	11583	1			T1	2		T5	27		T6	17
valid_sources[0x38]	8065	1			T5	13		T6	7		T9	4
valid_sources[0x39]	7121	1			T1	6		T5	13		T6	2
valid_sources[0x3a]	6577	1			T1	2		T5	24		T6	15
valid_sources[0x3b]	11366	1			T1	2		T5	3		T6	13
valid_sources[0x3c]	10096	1			T1	2		T5	20		T6	7
valid_sources[0x3d]	10932	1			T1	4		T5	7		T6	10
valid_sources[0x3e]	6689	1			T1	8		T5	13		T6	13
valid_sources[0x3f]	7013	1			T1	2		T5	15		T6	18
valid_sources[0x40]	6800	1			T1	3		T5	8		T6	8
valid_sources[0x41]	19593	1			T1	2		T5	11		T6	15
valid_sources[0x42]	7301	1			T1	3		T5	18		T6	24
valid_sources[0x43]	6580	1			T1	1		T5	33		T6	13
valid_sources[0x44]	7020	1			T1	10		T5	17		T6	19
valid_sources[0x45]	6893	1			T1	11		T5	9		T6	23
valid_sources[0x46]	6852	1			T5	24		T6	13		T9	1
valid_sources[0x47]	6719	1			T1	4		T5	28		T6	13
valid_sources[0x48]	6973	1			T1	8		T5	33		T6	14
valid_sources[0x49]	10532	1			T5	12		T6	15		T9	15
valid_sources[0x4a]	11060	1			T1	1		T5	36		T6	20
valid_sources[0x4b]	8114	1			T1	20		T5	12		T6	29
valid_sources[0x4c]	7215	1			T1	2		T5	9		T6	25
valid_sources[0x4d]	9575	1			T1	2		T5	18		T6	43
valid_sources[0x4e]	7329	1			T5	18		T6	27		T9	5
valid_sources[0x4f]	7017	1			T1	12		T5	22		T6	16
valid_sources[0x50]	7049	1			T1	4		T5	17		T6	5
valid_sources[0x51]	6850	1			T5	12		T6	33		T16	19
valid_sources[0x52]	6651	1			T1	4		T5	9		T6	12
valid_sources[0x53]	18708	1			T1	6		T5	12		T6	19
valid_sources[0x54]	11462	1			T1	3		T5	17		T6	22
valid_sources[0x55]	11329	1			T1	4		T5	13		T6	13
valid_sources[0x56]	7582	1			T5	26		T6	22		T9	6
valid_sources[0x57]	8187	1			T1	7		T5	16		T6	19
valid_sources[0x58]	11855	1			T1	5		T5	24		T6	19
valid_sources[0x59]	8117	1			T1	5		T5	15		T6	23
valid_sources[0x5a]	7380	1			T2	1		T5	37		T6	22
valid_sources[0x5b]	17621	1			T1	2		T5	11		T6	27
valid_sources[0x5c]	13829	1			T1	6		T5	12		T6	17
valid_sources[0x5d]	11405	1			T1	10		T5	8		T6	11
valid_sources[0x5e]	8277	1			T1	5		T5	20		T6	33
valid_sources[0x5f]	6730	1			T5	14		T6	11		T10	7
valid_sources[0x60]	7173	1			T1	3		T5	8		T6	6
valid_sources[0x61]	15241	1			T1	11		T5	8		T6	21
valid_sources[0x62]	11345	1			T1	2		T5	35		T6	15
valid_sources[0x63]	7104	1			T5	13		T6	9		T7	3
valid_sources[0x64]	6777	1			T1	8		T5	14		T6	8
valid_sources[0x65]	8808	1			T1	4		T5	16		T6	12
valid_sources[0x66]	10476	1			T5	29		T6	24		T7	2
valid_sources[0x67]	7111	1			T5	5		T6	21		T10	5
valid_sources[0x68]	9584	1			T1	12		T5	17		T6	9
valid_sources[0x69]	11556	1			T5	15		T6	11		T9	16
valid_sources[0x6a]	7018	1			T5	11		T6	8		T10	9
valid_sources[0x6b]	7987	1			T1	7		T5	24		T6	13
valid_sources[0x6c]	6940	1			T2	2		T5	23		T6	20
valid_sources[0x6d]	11244	1			T1	3		T5	15		T6	21
valid_sources[0x6e]	7990	1			T1	4		T5	11		T6	6
valid_sources[0x6f]	11415	1			T1	3		T5	13		T6	14
valid_sources[0x70]	7796	1			T1	1		T5	21		T6	8
valid_sources[0x71]	8101	1			T5	14		T6	18		T9	19
valid_sources[0x72]	11383	1			T1	4		T6	11		T9	4
valid_sources[0x73]	7028	1			T1	5		T5	27		T6	12
valid_sources[0x74]	6823	1			T1	8		T5	50		T6	8
valid_sources[0x75]	7722	1			T1	1		T5	22		T6	11
valid_sources[0x76]	7247	1			T1	3		T5	18		T6	14
valid_sources[0x77]	8218	1			T1	3		T5	8		T6	13
valid_sources[0x78]	7185	1			T5	11		T6	19		T9	3
valid_sources[0x79]	20594	1			T5	4		T6	16		T9	13
valid_sources[0x7a]	7002	1			T5	23		T6	22		T11	38
valid_sources[0x7b]	11226	1			T5	7		T6	6		T9	22
valid_sources[0x7c]	6763	1			T1	5		T5	1		T6	36
valid_sources[0x7d]	6514	1			T1	3		T5	26		T6	4
valid_sources[0x7e]	8113	1			T1	1		T5	7		T6	13
valid_sources[0x7f]	8677	1			T1	1		T5	14		T6	14
valid_sources[0x80]	6804	1			T1	5		T5	25		T6	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1038870

1

T1

808

T3

36

T4

45

values[0x0]

all_enables

biggest_size

79952

1

T1

58

T2

5

T3

12

values[0x1]

all_enables

biggest_size

57798

1

T1

35

T2

9

T3

6