Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30099	1			T1	11		T5	7		T6	19
auto[PWRUP]	133	1			T9	2		T60	2		T61	5
auto[ONEST_0]	70	1			T9	1		T60	3		T61	1
auto[ONEST_021]	10	1			T201	1		T202	1		T203	1
auto[ONEST_1]	78	1			T9	1		T60	3		T62	1
auto[ONEST_DONE]	6	1			T63	1		T204	1		T205	1
auto[LP_0]	123	1			T9	2		T61	3		T62	1
auto[LP_021]	28	1			T60	1		T46	1		T64	1
auto[LP_1]	125	1			T9	3		T61	2		T63	4
auto[LP_EVAL]	63	1			T60	1		T62	1		T64	3
auto[LP_SLP]	503	1			T9	9		T60	5		T61	7
auto[LP_PWRUP]	25	1			T202	4		T206	1		T207	1
auto[NP_0]	166	1			T9	3		T60	2		T61	3
auto[NP_021]	38	1			T9	1		T61	2		T63	1
auto[NP_1]	142	1			T9	3		T60	3		T61	1
auto[NP_EVAL]	41	1			T61	3		T62	1		T63	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T62

1

T46

1

T198

1

min

29553

1

T1

11

T5

7

T6

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29562	1			T1	11		T5	7		T6	19
pow[0x1]	9	1			T18	1		T208	1		T209	1
pow[0x2]	14	1			T61	3		T206	1		T210	1
pow[0x3]	29	1			T62	1		T63	1		T64	3
pow[0x4]	62	1			T9	1		T60	1		T61	1
pow[0x5]	140	1			T9	3		T60	2		T61	1
pow[0x6]	279	1			T9	4		T60	5		T61	5
pow[0x7]	484	1			T9	4		T60	5		T61	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

211

1

T9

3

T61

1

T63

5

min

29094

1

T1

11

T5

7

T6

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29094	1			T1	11		T5	7		T6	19
pow[0x7]	2	1			T63	1		T211	1		-	-
pow[0x8]	2	1			T207	1		T212	1		-	-
pow[0x9]	5	1			T213	1		T207	1		T214	1
pow[0xa]	26	1			T61	1		T63	2		T64	1
pow[0xb]	43	1			T46	1		T215	1		T198	1
pow[0xc]	85	1			T9	1		T61	2		T63	1
pow[0xd]	122	1			T9	3		T61	2		T62	2
pow[0xe]	285	1			T9	7		T61	5		T62	1
pow[0xf]	592	1			T9	14		T60	10		T61	8