Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2333	1			T9	42		T60	16		T61	7
auto[PWRUP]	151	1			T9	3		T61	1		T63	1
auto[ONEST_0]	89	1			T60	1		T61	4		T62	2
auto[ONEST_021]	27	1			T60	1		T61	1		T39	1
auto[ONEST_1]	87	1			T9	2		T60	1		T61	1
auto[ONEST_DONE]	3	1			T46	1		T196	1		T324	1
auto[LP_0]	156	1			T9	3		T60	2		T61	2
auto[LP_021]	22	1			T9	1		T60	1		T215	1
auto[LP_1]	150	1			T9	2		T60	1		T62	2
auto[LP_EVAL]	62	1			T60	1		T39	1		T215	1
auto[LP_SLP]	537	1			T9	12		T60	5		T61	3
auto[LP_PWRUP]	34	1			T9	1		T60	1		T62	1
auto[NP_0]	232	1			T9	2		T60	3		T61	3
auto[NP_021]	47	1			T61	1		T46	1		T41	1
auto[NP_1]	231	1			T9	5		T60	1		T63	2
auto[NP_EVAL]	33	1			T9	1		T39	1		T64	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T169

1

T214

1

T208

1

min

1968

1

T9

19

T60

12

T61

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1987	1			T9	19		T60	12		T61	4
pow[0x1]	13	1			T63	1		T169	1		T100	1
pow[0x2]	26	1			T9	3		T61	1		T46	1
pow[0x3]	39	1			T9	3		T60	1		T63	2
pow[0x4]	63	1			T9	1		T60	1		T63	2
pow[0x5]	137	1			T9	3		T60	1		T61	4
pow[0x6]	268	1			T9	8		T61	2		T62	1
pow[0x7]	559	1			T9	16		T60	4		T61	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

187

1

T9

5

T62

3

T63

3

min

1380

1

T9

7

T60

3

T61

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1387	1			T9	7		T60	3		T61	2
pow[0x1]	17	1			T40	1		T42	2		T43	1
pow[0x2]	15	1			T40	1		T18	1		T19	2
pow[0x3]	40	1			T39	3		T40	1		T41	1
pow[0x4]	58	1			T39	2		T41	2		T17	4
pow[0x5]	1	1			T325	1		-	-		-	-
pow[0x6]	1	1			T326	1		-	-		-	-
pow[0x7]	2	1			T60	1		T24	1		-	-
pow[0x8]	10	1			T60	1		T63	1		T46	1
pow[0x9]	13	1			T213	1		T202	1		T206	1
pow[0xa]	27	1			T60	1		T61	1		T46	1
pow[0xb]	38	1			T62	1		T64	1		T169	1
pow[0xc]	68	1			T9	1		T60	1		T61	1
pow[0xd]	148	1			T9	1		T60	5		T62	1
pow[0xe]	278	1			T9	11		T60	5		T61	2
pow[0xf]	632	1			T9	21		T60	2		T61	3