Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T12
0	1	Covered	T5,T6,T12
1	0	Covered	T5,T6,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T6,T8,T14
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T14
0	1	Covered	T6,T8,T14
1	0	Covered	T6,T8,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T6,T13,T14
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T13,T14
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T13,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T14,T15
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T15
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T14,T15

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T14
0	1	Covered	T1,T6,T14
1	0	Covered	T1,T6,T14

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T6,T8,T14
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T14
0	1	Covered	T6,T8,T14
1	0	Covered	T6,T8,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T6,T13,T14
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T13,T14
0	1	Covered	T6,T13,T14
1	0	Covered	T6,T13,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T14,T15
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T15
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T14,T15

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T14
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T14
0	1	Covered	T1,T6,T14
1	0	Covered	T1,T6,T14

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T6,T10,T11
1	1	1	Covered	T1,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T11
0	1	Covered	T6,T9,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T9,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T1,T6,T10
1	1	1	Covered	T1,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T8
1	1	0	Covered	T5,T6,T8
1	1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T8
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T10
1	1	0	Covered	T1,T5,T10
1	1	1	Covered	T1,T5,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T1,T5,T6
1	1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T8,T10
1	1	0	Covered	T6,T8,T10
1	1	1	Covered	T6,T8,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T10
1	1	0	Covered	T1,T6,T10
1	1	1	Covered	T1,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T8,T10
1	1	0	Covered	T6,T8,T10
1	1	1	Covered	T6,T8,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T6,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T6,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T5,T6
1	1	Covered	T5,T6,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T6,T8
1	1	Covered	T1,T5,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T8,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T6,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T5,T6
1	1	Covered	T6,T8,T10

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T14,T59
1	0	Covered	T5,T6,T11

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T58
1	0	Covered	T6,T11,T13
1	1	Covered	T5,T14,T59

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T4,T7
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T14

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T13,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T13,T14

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T14,T15

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T14,T15

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T14

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T14

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T6,T8

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	35822507	35499636	0	0
gen_filter_match[0].MatchCheck00_A	35822507	11505239	0	0
gen_filter_match[0].MatchCheck01_A	35822507	2251172	0	0
gen_filter_match[0].MatchCheck10_A	35822507	3237531	0	0
gen_filter_match[0].MatchCheck11_A	35822507	18505694	0	0
gen_filter_match[1].MatchCheck00_A	35822507	12025216	0	0
gen_filter_match[1].MatchCheck01_A	35822507	1506394	0	0
gen_filter_match[1].MatchCheck10_A	35822507	1617844	0	0
gen_filter_match[1].MatchCheck11_A	35822507	20350182	0	0
gen_filter_match[2].MatchCheck00_A	35822507	13475250	0	0
gen_filter_match[2].MatchCheck01_A	35822507	772567	0	0
gen_filter_match[2].MatchCheck10_A	35822507	635871	0	0
gen_filter_match[2].MatchCheck11_A	35822507	20615948	0	0
gen_filter_match[3].MatchCheck00_A	35822507	13964331	0	0
gen_filter_match[3].MatchCheck01_A	35822507	283576	0	0
gen_filter_match[3].MatchCheck10_A	35822507	465474	0	0
gen_filter_match[3].MatchCheck11_A	35822507	20786255	0	0
gen_filter_match[4].MatchCheck00_A	35822507	14229524	0	0
gen_filter_match[4].MatchCheck01_A	35822507	33085	0	0
gen_filter_match[4].MatchCheck10_A	35822507	103842	0	0
gen_filter_match[4].MatchCheck11_A	35822507	21133185	0	0
gen_filter_match[5].MatchCheck00_A	35822507	14057199	0	0
gen_filter_match[5].MatchCheck01_A	35822507	72178	0	0
gen_filter_match[5].MatchCheck10_A	35822507	68618	0	0
gen_filter_match[5].MatchCheck11_A	35822507	21301641	0	0
gen_filter_match[6].MatchCheck00_A	35822507	12782935	0	0
gen_filter_match[6].MatchCheck01_A	35822507	69173	0	0
gen_filter_match[6].MatchCheck10_A	35822507	46753	0	0
gen_filter_match[6].MatchCheck11_A	35822507	22600775	0	0
gen_filter_match[7].MatchCheck00_A	35822507	14369247	0	0
gen_filter_match[7].MatchCheck01_A	35822507	310326	0	0
gen_filter_match[7].MatchCheck10_A	35822507	183673	0	0
gen_filter_match[7].MatchCheck11_A	35822507	20636390	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	35499636	0	0
T1	65189	65111	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	104945	0	0
T7	658	607	0	0
T8	33005	32931	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	11505239	0	0
T1	65189	32466	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	72177	0	0
T7	658	607	0	0
T8	33005	32931	0	0
T9	37593	30956	0	0
T16	90	10	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	2251172	0	0
T13	35309	35222	0	0
T14	115463	0	0	0
T15	69046	0	0	0
T31	0	1	0	0
T33	0	68522	0	0
T44	0	32979	0	0
T58	64545	32837	0	0
T59	120786	0	0	0
T60	19719	0	0	0
T61	15587	0	0	0
T62	16304	0	0	0
T110	0	33192	0	0
T141	32794	0	0	0
T142	0	33239	0	0
T143	0	32263	0	0
T144	0	33907	0	0
T145	0	34049	0	0
T146	67190	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	3237531	0	0
T1	65189	32645	0	0
T2	4447	0	0	0
T3	1141	0	0	0
T4	1198	0	0	0
T5	34532	0	0	0
T6	105038	0	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T16	90	0	0	0
T46	0	33155	0	0
T47	0	37994	0	0
T52	0	34470	0	0
T70	0	39495	0	0
T95	0	33269	0	0
T142	0	33131	0	0
T147	0	31728	0	0
T148	0	1	0	0
T149	0	33558	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	18505694	0	0
T6	105038	32768	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	815	0	0
T10	65841	65755	0	0
T11	122291	122226	0	0
T12	32934	0	0	0
T13	35309	0	0	0
T14	0	82041	0	0
T15	0	32827	0	0
T16	90	0	0	0
T57	68	0	0	0
T59	0	120707	0	0
T60	0	467	0	0
T61	0	883	0	0
T62	0	642	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	12025216	0	0
T1	65189	32466	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	4	0	0
T7	658	607	0	0
T8	33005	32931	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	1506394	0	0
T6	105038	32815	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	65841	0	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T13	35309	0	0	0
T16	90	0	0	0
T44	0	36027	0	0
T55	0	32523	0	0
T57	68	0	0	0
T70	0	33408	0	0
T150	0	32740	0	0
T151	0	33786	0	0
T152	0	35909	0	0
T153	0	32309	0	0
T154	0	33785	0	0
T155	0	70620	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	1617844	0	0
T15	69046	36132	0	0
T39	12379	0	0	0
T40	0	337	0	0
T42	0	5785	0	0
T52	0	33840	0	0
T58	64545	0	0	0
T59	120786	0	0	0
T60	19719	0	0	0
T61	15587	0	0	0
T62	16304	0	0	0
T63	24391	0	0	0
T69	0	38351	0	0
T98	0	35858	0	0
T141	32794	0	0	0
T142	0	1	0	0
T144	0	39979	0	0
T146	67190	0	0	0
T148	0	1	0	0
T156	0	36969	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	20350182	0	0
T1	65189	32645	0	0
T2	4447	0	0	0
T3	1141	0	0	0
T4	1198	0	0	0
T5	34532	0	0	0
T6	105038	72126	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	0	65755	0	0
T11	0	122226	0	0
T12	0	32867	0	0
T13	0	35222	0	0
T14	0	33322	0	0
T15	0	32827	0	0
T16	90	0	0	0
T58	0	32837	0	0
T146	0	67117	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	13475250	0	0
T1	65189	65111	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	3	0	0
T6	105038	32819	0	0
T7	658	607	0	0
T8	33005	3	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	772567	0	0
T31	0	34497	0	0
T34	0	32327	0	0
T42	11310	0	0	0
T144	107123	1	0	0
T145	100126	0	0	0
T151	0	1	0	0
T157	0	35997	0	0
T158	0	33668	0	0
T159	0	33283	0	0
T160	0	34868	0	0
T161	0	32811	0	0
T162	0	1	0	0
T163	67	0	0	0
T164	39738	0	0	0
T165	120671	0	0	0
T166	23999	0	0	0
T167	103161	0	0	0
T168	1174	0	0	0
T169	21700	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	635871	0	0
T5	34532	1	0	0
T6	105038	39358	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	65841	0	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T16	90	0	0	0
T57	68	0	0	0
T107	0	31296	0	0
T108	0	35063	0	0
T113	0	37935	0	0
T144	0	1	0	0
T146	0	33934	0	0
T148	0	1	0	0
T167	0	36283	0	0
T170	0	32081	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	20615948	0	0
T5	34532	34461	0	0
T6	105038	32768	0	0
T7	658	0	0	0
T8	33005	32928	0	0
T9	37593	0	0	0
T10	65841	65755	0	0
T11	122291	122226	0	0
T12	32934	32867	0	0
T14	0	115363	0	0
T15	0	68959	0	0
T16	90	0	0	0
T57	68	0	0	0
T58	0	32837	0	0
T59	0	120707	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	13964331	0	0
T1	65189	32649	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	3	0	0
T6	105038	104945	0	0
T7	658	607	0	0
T8	33005	32931	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	283576	0	0
T31	0	2	0	0
T41	14735	0	0	0
T84	78	0	0	0
T108	104756	1	0	0
T109	32639	0	0	0
T110	99903	0	0	0
T111	927	0	0	0
T112	100221	0	0	0
T113	104036	0	0	0
T124	0	34233	0	0
T144	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T171	0	32122	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	33683	0	0
T175	803	0	0	0
T176	91	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	465474	0	0
T5	34532	2	0	0
T6	105038	0	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	65841	0	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T16	90	0	0	0
T46	0	33154	0	0
T57	68	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T108	0	1	0	0
T112	0	32804	0	0
T142	0	2	0	0
T144	0	2	0	0
T148	0	1	0	0
T177	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	20786255	0	0
T1	65189	32462	0	0
T2	4447	0	0	0
T3	1141	0	0	0
T4	1198	0	0	0
T5	34532	34460	0	0
T6	105038	0	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	0	65755	0	0
T11	0	122226	0	0
T15	0	32827	0	0
T16	90	0	0	0
T39	0	3528	0	0
T58	0	31635	0	0
T59	0	120707	0	0
T141	0	32691	0	0
T146	0	33183	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	14229524	0	0
T1	65189	32649	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	4	0	0
T6	105038	39362	0	0
T7	658	607	0	0
T8	33005	3	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	33085	0	0
T31	0	1	0	0
T42	11310	0	0	0
T43	131042	0	0	0
T145	100126	33075	0	0
T153	0	1	0	0
T164	39738	0	0	0
T165	120671	0	0	0
T166	23999	0	0	0
T167	103161	0	0	0
T168	1174	0	0	0
T169	21700	0	0	0
T173	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	102747	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	103842	0	0
T5	34532	1	0	0
T6	105038	0	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	65841	0	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T16	90	0	0	0
T31	0	2	0	0
T43	0	3	0	0
T57	68	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T108	0	1	0	0
T142	0	2	0	0
T148	0	1	0	0
T177	0	1	0	0
T185	0	32656	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	21133185	0	0
T1	65189	32462	0	0
T2	4447	0	0	0
T3	1141	0	0	0
T4	1198	0	0	0
T5	34532	34460	0	0
T6	105038	65583	0	0
T7	658	0	0	0
T8	33005	32928	0	0
T9	37593	0	0	0
T10	0	65755	0	0
T11	0	122226	0	0
T13	0	35222	0	0
T14	0	75842	0	0
T15	0	32827	0	0
T16	90	0	0	0
T146	0	33183	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	14057199	0	0
T1	65189	65111	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	65587	0	0
T7	658	607	0	0
T8	33005	3	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	72178	0	0
T31	0	2	0	0
T98	113202	1	0	0
T99	37896	0	0	0
T108	0	1	0	0
T118	0	32613	0	0
T147	107820	0	0	0
T148	33052	0	0	0
T149	98492	0	0	0
T155	0	1	0	0
T173	0	1	0	0
T177	32349	0	0	0
T178	0	2	0	0
T179	0	2	0	0
T180	0	1	0	0
T186	0	2	0	0
T187	120049	0	0	0
T188	738	0	0	0
T189	78377	0	0	0
T190	33728	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	68618	0	0
T12	32934	1	0	0
T13	35309	0	0	0
T14	115463	0	0	0
T15	69046	0	0	0
T31	0	2	0	0
T43	0	1	0	0
T58	64545	0	0	0
T59	120786	0	0	0
T60	19719	0	0	0
T61	15587	0	0	0
T62	16304	0	0	0
T98	0	1	0	0
T108	0	32659	0	0
T142	0	1	0	0
T146	67190	0	0	0
T148	0	1	0	0
T150	0	1	0	0
T177	0	1	0	0
T191	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	21301641	0	0
T6	105038	39358	0	0
T7	658	0	0	0
T8	33005	32928	0	0
T9	37593	0	0	0
T10	65841	65755	0	0
T11	122291	122226	0	0
T12	32934	32866	0	0
T13	35309	35222	0	0
T14	0	72843	0	0
T15	0	32827	0	0
T16	90	0	0	0
T57	68	0	0	0
T58	0	32837	0	0
T59	0	120707	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	12782935	0	0
T1	65189	4	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	32772	0	0
T7	658	607	0	0
T8	33005	32931	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	69173	0	0
T31	0	1	0	0
T39	12379	0	0	0
T44	102486	0	0	0
T45	1226	0	0	0
T46	124104	0	0	0
T47	70882	0	0	0
T58	64545	0	0	0
T59	120786	0	0	0
T63	24391	0	0	0
T141	32794	0	0	0
T142	0	2	0	0
T146	67190	33183	0	0
T150	0	1	0	0
T153	0	1	0	0
T162	0	1	0	0
T172	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0
T193	0	35977	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	46753	0	0
T10	65841	1	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T13	35309	0	0	0
T14	115463	0	0	0
T15	69046	0	0	0
T43	0	7	0	0
T57	68	0	0	0
T60	19719	0	0	0
T61	15587	0	0	0
T62	16304	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T108	0	1	0	0
T142	0	2	0	0
T144	0	1	0	0
T148	0	1	0	0
T177	0	1	0	0
T194	0	2	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	22600775	0	0
T1	65189	65107	0	0
T2	4447	0	0	0
T3	1141	0	0	0
T4	1198	0	0	0
T5	34532	0	0	0
T6	105038	72173	0	0
T7	658	0	0	0
T8	33005	0	0	0
T9	37593	0	0	0
T10	0	65754	0	0
T11	0	122226	0	0
T13	0	35222	0	0
T14	0	39521	0	0
T15	0	36132	0	0
T16	90	0	0	0
T58	0	31635	0	0
T59	0	120707	0	0
T146	0	33934	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	14369247	0	0
T1	65189	65111	0	0
T2	4447	4370	0	0
T3	1141	1055	0	0
T4	1198	1109	0	0
T5	34532	34465	0	0
T6	105038	32772	0	0
T7	658	607	0	0
T8	33005	3	0	0
T9	37593	31771	0	0
T16	90	10	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	310326	0	0
T31	0	2	0	0
T33	0	1	0	0
T43	0	6579	0	0
T144	107123	1	0	0
T145	100126	0	0	0
T153	0	1	0	0
T163	67	0	0	0
T164	39738	0	0	0
T170	103974	0	0	0
T172	0	1	0	0
T178	0	36186	0	0
T194	0	33734	0	0
T195	99238	33779	0	0
T196	0	166248	0	0
T197	64331	0	0	0
T198	16533	0	0	0
T199	1197	0	0	0
T200	65798	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	183673	0	0
T10	65841	1	0	0
T11	122291	0	0	0
T12	32934	0	0	0
T13	35309	0	0	0
T14	115463	0	0	0
T15	69046	0	0	0
T29	0	1	0	0
T31	0	2	0	0
T40	0	2612	0	0
T41	0	1	0	0
T42	0	2	0	0
T57	68	0	0	0
T60	19719	0	0	0
T61	15587	0	0	0
T62	16304	0	0	0
T108	0	1	0	0
T144	0	1	0	0
T148	0	1	0	0
T177	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35822507	20636390	0	0
T6	105038	72173	0	0
T7	658	0	0	0
T8	33005	32928	0	0
T9	37593	0	0	0
T10	65841	65754	0	0
T11	122291	122226	0	0
T12	32934	0	0	0
T13	35309	0	0	0
T14	0	82041	0	0
T15	0	32827	0	0
T16	90	0	0	0
T39	0	3528	0	0
T44	0	36027	0	0
T57	68	0	0	0
T59	0	120707	0	0
T141	0	32691	0	0