Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1839	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1787	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1822	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1939	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1863	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1819	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2011	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1819	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1917	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1860	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1750	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1938	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1872	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1912	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1756	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1686	0	0
adc_en_ctl_rd_A	2147483647	1523	0	0
adc_fsm_rst_rd_A	2147483647	1532	0	0
adc_intr_ctl_rd_A	2147483647	1883	0	0
adc_lp_sample_ctl_rd_A	2147483647	1518	0	0
adc_pd_ctl_rd_A	2147483647	1760	0	0
adc_sample_ctl_rd_A	2147483647	1425	0	0
adc_wakeup_ctl_rd_A	2147483647	1658	0	0
intr_enable_rd_A	2147483647	1899	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1839	0	0
T17	368933	42	0	0
T18	0	25	0	0
T19	0	38	0	0
T20	0	25	0	0
T21	0	13	0	0
T22	0	35	0	0
T23	0	14	0	0
T24	0	37	0	0
T25	0	3	0	0
T26	0	22	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1787	0	0
T17	368933	26	0	0
T18	0	30	0	0
T19	0	41	0	0
T20	0	15	0	0
T21	0	2	0	0
T22	0	25	0	0
T23	0	10	0	0
T24	0	36	0	0
T25	0	9	0	0
T26	0	26	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1822	0	0
T17	368933	41	0	0
T18	0	26	0	0
T19	0	34	0	0
T20	0	16	0	0
T22	0	15	0	0
T23	0	17	0	0
T24	0	33	0	0
T25	0	5	0	0
T26	0	21	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0
T36	0	35	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1939	0	0
T17	368933	36	0	0
T18	0	17	0	0
T19	0	31	0	0
T20	0	13	0	0
T21	0	11	0	0
T22	0	47	0	0
T23	0	21	0	0
T24	0	39	0	0
T25	0	6	0	0
T26	0	9	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1863	0	0
T17	368933	36	0	0
T18	0	24	0	0
T19	0	16	0	0
T20	0	20	0	0
T21	0	9	0	0
T22	0	44	0	0
T23	0	34	0	0
T24	0	27	0	0
T25	0	14	0	0
T26	0	24	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1819	0	0
T17	368933	45	0	0
T18	0	12	0	0
T19	0	37	0	0
T20	0	34	0	0
T21	0	10	0	0
T22	0	23	0	0
T23	0	13	0	0
T24	0	35	0	0
T25	0	4	0	0
T26	0	17	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2011	0	0
T17	368933	33	0	0
T18	0	33	0	0
T19	0	28	0	0
T20	0	23	0	0
T21	0	15	0	0
T22	0	43	0	0
T23	0	15	0	0
T24	0	36	0	0
T25	0	12	0	0
T26	0	16	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1819	0	0
T17	368933	41	0	0
T18	0	11	0	0
T19	0	17	0	0
T20	0	15	0	0
T21	0	9	0	0
T22	0	11	0	0
T23	0	17	0	0
T24	0	36	0	0
T25	0	7	0	0
T26	0	16	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1917	0	0
T17	368933	37	0	0
T18	0	19	0	0
T19	0	33	0	0
T20	0	38	0	0
T21	0	7	0	0
T22	0	33	0	0
T23	0	15	0	0
T24	0	40	0	0
T25	0	6	0	0
T26	0	16	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1860	0	0
T17	368933	34	0	0
T18	0	48	0	0
T19	0	40	0	0
T20	0	27	0	0
T21	0	4	0	0
T22	0	24	0	0
T23	0	27	0	0
T24	0	33	0	0
T25	0	17	0	0
T26	0	18	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1750	0	0
T17	368933	37	0	0
T18	0	26	0	0
T19	0	32	0	0
T20	0	18	0	0
T21	0	3	0	0
T22	0	28	0	0
T23	0	26	0	0
T24	0	42	0	0
T25	0	5	0	0
T26	0	11	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1938	0	0
T17	368933	30	0	0
T18	0	14	0	0
T19	0	27	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	0	33	0	0
T25	0	2	0	0
T26	0	21	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872	0	0
T17	368933	33	0	0
T18	0	41	0	0
T19	0	27	0	0
T20	0	14	0	0
T21	0	12	0	0
T22	0	38	0	0
T23	0	13	0	0
T24	0	49	0	0
T25	0	7	0	0
T26	0	6	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1912	0	0
T17	368933	32	0	0
T18	0	22	0	0
T19	0	26	0	0
T20	0	27	0	0
T21	0	8	0	0
T22	0	20	0	0
T23	0	23	0	0
T24	0	38	0	0
T25	0	22	0	0
T26	0	20	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1756	0	0
T17	368933	33	0	0
T18	0	19	0	0
T19	0	18	0	0
T20	0	15	0	0
T21	0	6	0	0
T22	0	34	0	0
T23	0	18	0	0
T24	0	40	0	0
T25	0	6	0	0
T26	0	9	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1686	0	0
T17	368933	36	0	0
T18	0	32	0	0
T19	0	34	0	0
T20	0	33	0	0
T21	0	14	0	0
T22	0	27	0	0
T23	0	21	0	0
T24	0	46	0	0
T25	0	7	0	0
T26	0	18	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T17	368933	28	0	0
T18	0	16	0	0
T19	0	19	0	0
T20	0	14	0	0
T21	0	4	0	0
T22	0	32	0	0
T23	0	18	0	0
T24	0	31	0	0
T25	0	1	0	0
T26	0	22	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1532	0	0
T17	368933	38	0	0
T18	0	32	0	0
T19	0	13	0	0
T20	0	14	0	0
T21	0	20	0	0
T22	0	31	0	0
T23	0	19	0	0
T24	0	47	0	0
T25	0	13	0	0
T26	0	35	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1883	0	0
T17	368933	40	0	0
T18	0	22	0	0
T19	0	23	0	0
T20	0	9	0	0
T21	0	4	0	0
T22	0	21	0	0
T23	0	15	0	0
T24	0	43	0	0
T25	0	17	0	0
T26	0	28	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1518	0	0
T17	368933	39	0	0
T18	0	33	0	0
T19	0	33	0	0
T20	0	8	0	0
T21	0	8	0	0
T22	0	7	0	0
T23	0	24	0	0
T24	0	33	0	0
T25	0	21	0	0
T26	0	6	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T17	368933	43	0	0
T18	0	18	0	0
T19	0	22	0	0
T20	0	30	0	0
T21	0	3	0	0
T22	0	27	0	0
T23	0	9	0	0
T24	0	31	0	0
T25	0	8	0	0
T26	0	29	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425	0	0
T17	368933	42	0	0
T18	0	19	0	0
T19	0	30	0	0
T20	0	25	0	0
T21	0	10	0	0
T22	0	13	0	0
T23	0	19	0	0
T24	0	42	0	0
T26	0	9	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0
T36	0	20	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1658	0	0
T17	368933	38	0	0
T18	0	38	0	0
T19	0	43	0	0
T20	0	20	0	0
T21	0	8	0	0
T22	0	19	0	0
T23	0	10	0	0
T24	0	42	0	0
T25	0	12	0	0
T26	0	7	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
T31	415151	0	0	0
T32	818464	0	0	0
T33	445782	0	0	0
T34	793722	0	0	0
T35	690720	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1899	0	0
T17	368933	31	0	0
T18	0	31	0	0
T19	0	46	0	0
T20	0	26	0	0
T21	0	21	0	0
T22	0	42	0	0
T23	0	24	0	0
T24	0	39	0	0
T27	75148	0	0	0
T28	433577	0	0	0
T29	839936	0	0	0
T30	661271	0	0	0
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T33	445782	0	0	0
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T35	690720	0	0	0
T37	0	19	0	0
T38	0	9	0	0