Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1179804	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1152055

1

T4

3

T1

473

T2

4302

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2046407	1			T4	1		T2	8094		T3	872
values[0x0]	141907	1			T4	6		T1	585		T2	262
values[0x1]	143545	1			T4	3		T1	572		T2	267

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	943639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1388220

1

T4

3

T1

576

T2

5172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6873	1			T2	46		T5	41		T7	3
valid_sources[0x01]	8594	1			T1	7		T2	54		T7	2
valid_sources[0x02]	15235	1			T2	38		T5	9		T6	1
valid_sources[0x03]	11428	1			T1	20		T2	35		T5	10
valid_sources[0x04]	8890	1			T2	26		T5	22		T7	3
valid_sources[0x05]	6596	1			T2	33		T5	9		T7	11
valid_sources[0x06]	11358	1			T1	58		T2	66		T5	34
valid_sources[0x07]	7801	1			T2	27		T5	8		T7	12
valid_sources[0x08]	6645	1			T1	16		T2	30		T5	25
valid_sources[0x09]	6704	1			T2	24		T5	5		T7	32
valid_sources[0x0a]	10731	1			T2	24		T5	17		T7	22
valid_sources[0x0b]	16713	1			T2	43		T5	3		T7	8
valid_sources[0x0c]	7051	1			T2	41		T5	2		T7	3
valid_sources[0x0d]	11242	1			T2	16		T5	9		T7	17
valid_sources[0x0e]	9851	1			T2	47		T5	9		T7	12
valid_sources[0x0f]	7487	1			T2	41		T5	15		T8	3
valid_sources[0x10]	7838	1			T2	34		T5	9		T7	11
valid_sources[0x11]	15385	1			T2	30		T5	9		T7	20
valid_sources[0x12]	18505	1			T2	24		T5	8		T7	6
valid_sources[0x13]	7363	1			T1	21		T2	20		T5	16
valid_sources[0x14]	12096	1			T2	24		T5	10		T7	2
valid_sources[0x15]	6801	1			T2	42		T5	8		T7	2
valid_sources[0x16]	16001	1			T2	16		T5	6		T7	1
valid_sources[0x17]	7844	1			T1	5		T2	40		T5	9
valid_sources[0x18]	7307	1			T2	7		T5	6		T7	6
valid_sources[0x19]	9270	1			T2	33		T5	8		T7	4
valid_sources[0x1a]	7591	1			T2	22		T5	12		T7	9
valid_sources[0x1b]	12204	1			T2	39		T3	964		T5	2
valid_sources[0x1c]	12011	1			T2	36		T7	20		T8	1
valid_sources[0x1d]	6915	1			T2	24		T5	9		T7	26
valid_sources[0x1e]	7240	1			T2	44		T5	14		T7	7
valid_sources[0x1f]	11375	1			T1	17		T2	22		T7	2
valid_sources[0x20]	6670	1			T2	13		T5	8		T7	6
valid_sources[0x21]	7971	1			T2	19		T5	2		T11	15
valid_sources[0x22]	10061	1			T2	32		T5	3		T8	2
valid_sources[0x23]	7138	1			T1	55		T2	24		T5	15
valid_sources[0x24]	12620	1			T4	1		T2	22		T5	18
valid_sources[0x25]	11169	1			T2	31		T5	2		T11	18
valid_sources[0x26]	8516	1			T2	30		T5	2		T7	18
valid_sources[0x27]	6859	1			T2	62		T5	3		T8	9
valid_sources[0x28]	7258	1			T2	24		T5	18		T8	5
valid_sources[0x29]	7043	1			T2	38		T5	13		T7	16
valid_sources[0x2a]	6648	1			T4	1		T2	24		T5	10
valid_sources[0x2b]	6888	1			T1	38		T2	44		T5	10
valid_sources[0x2c]	6654	1			T2	27		T5	8		T7	4
valid_sources[0x2d]	7048	1			T2	31		T5	11		T7	5
valid_sources[0x2e]	6952	1			T4	1		T2	46		T5	12
valid_sources[0x2f]	6947	1			T1	7		T2	39		T5	10
valid_sources[0x30]	6770	1			T1	17		T2	41		T5	9
valid_sources[0x31]	8463	1			T1	2		T2	54		T5	1
valid_sources[0x32]	9629	1			T2	42		T5	24		T7	7
valid_sources[0x33]	7643	1			T2	49		T5	16		T7	4
valid_sources[0x34]	7871	1			T1	29		T2	12		T5	9
valid_sources[0x35]	11573	1			T2	53		T5	26		T7	8
valid_sources[0x36]	12441	1			T2	16		T5	7		T7	2
valid_sources[0x37]	6323	1			T2	50		T5	5		T7	30
valid_sources[0x38]	13029	1			T2	54		T5	13		T7	34
valid_sources[0x39]	15626	1			T2	20		T5	11		T7	8
valid_sources[0x3a]	7086	1			T2	34		T5	9		T7	1
valid_sources[0x3b]	15844	1			T2	43		T5	10		T8	6
valid_sources[0x3c]	7273	1			T1	9		T2	28		T5	11
valid_sources[0x3d]	9652	1			T2	48		T7	5		T11	13
valid_sources[0x3e]	7845	1			T1	19		T2	24		T5	21
valid_sources[0x3f]	6748	1			T2	39		T5	14		T7	4
valid_sources[0x40]	9972	1			T1	6		T2	68		T5	21
valid_sources[0x41]	6956	1			T1	14		T2	39		T5	12
valid_sources[0x42]	9012	1			T2	18		T5	15		T7	18
valid_sources[0x43]	9721	1			T1	17		T2	43		T5	6
valid_sources[0x44]	12174	1			T1	4		T2	71		T5	5
valid_sources[0x45]	11456	1			T2	14		T5	20		T7	4
valid_sources[0x46]	16080	1			T2	36		T7	1		T8	7
valid_sources[0x47]	6465	1			T2	6		T5	4		T7	10
valid_sources[0x48]	7849	1			T2	31		T5	5		T7	6
valid_sources[0x49]	9375	1			T2	54		T5	11		T7	6
valid_sources[0x4a]	11434	1			T2	29		T5	18		T8	7
valid_sources[0x4b]	10147	1			T2	66		T5	6		T7	4
valid_sources[0x4c]	6725	1			T2	27		T5	2		T7	8
valid_sources[0x4d]	10351	1			T1	15		T2	27		T5	22
valid_sources[0x4e]	10944	1			T2	37		T5	5		T7	5
valid_sources[0x4f]	6878	1			T1	6		T2	23		T5	17
valid_sources[0x50]	6887	1			T2	23		T5	20		T7	30
valid_sources[0x51]	12354	1			T2	29		T5	10		T7	2
valid_sources[0x52]	6592	1			T2	29		T5	5		T7	7
valid_sources[0x53]	18869	1			T2	15		T5	2		T7	13
valid_sources[0x54]	7986	1			T2	36		T5	10		T7	14
valid_sources[0x55]	7178	1			T2	54		T5	8		T7	16
valid_sources[0x56]	6655	1			T2	26		T5	15		T11	19
valid_sources[0x57]	7680	1			T2	41		T5	19		T7	8
valid_sources[0x58]	10979	1			T2	22		T5	10		T7	10
valid_sources[0x59]	7787	1			T1	10		T2	34		T5	4
valid_sources[0x5a]	6784	1			T2	53		T5	2		T7	21
valid_sources[0x5b]	6976	1			T2	49		T5	17		T7	8
valid_sources[0x5c]	6857	1			T2	35		T5	14		T7	4
valid_sources[0x5d]	11180	1			T2	60		T5	1		T7	27
valid_sources[0x5e]	6780	1			T2	71		T5	6		T7	11
valid_sources[0x5f]	10766	1			T2	21		T5	5		T8	9
valid_sources[0x60]	7462	1			T2	39		T5	12		T7	14
valid_sources[0x61]	11180	1			T2	15		T5	15		T7	19
valid_sources[0x62]	8510	1			T2	30		T5	19		T7	3
valid_sources[0x63]	6873	1			T2	39		T5	18		T7	5
valid_sources[0x64]	13462	1			T1	5		T2	55		T5	3
valid_sources[0x65]	6796	1			T1	30		T2	78		T5	4
valid_sources[0x66]	9336	1			T2	23		T5	12		T8	9
valid_sources[0x67]	6670	1			T2	35		T5	6		T8	1
valid_sources[0x68]	10198	1			T2	36		T5	11		T7	4
valid_sources[0x69]	12496	1			T2	10		T5	2		T7	4
valid_sources[0x6a]	6891	1			T2	39		T5	20		T7	10
valid_sources[0x6b]	6869	1			T1	16		T2	48		T5	6
valid_sources[0x6c]	11291	1			T2	34		T5	12		T11	17
valid_sources[0x6d]	7056	1			T2	36		T5	8		T7	10
valid_sources[0x6e]	7536	1			T1	5		T2	60		T5	4
valid_sources[0x6f]	7660	1			T4	2		T2	28		T5	13
valid_sources[0x70]	7074	1			T1	22		T2	42		T5	17
valid_sources[0x71]	11049	1			T2	14		T5	8		T7	19
valid_sources[0x72]	14482	1			T2	24		T5	16		T8	5
valid_sources[0x73]	14126	1			T2	17		T5	3		T8	3
valid_sources[0x74]	6823	1			T2	21		T5	9		T7	11
valid_sources[0x75]	7520	1			T2	17		T5	15		T11	13
valid_sources[0x76]	9770	1			T1	21		T2	36		T5	29
valid_sources[0x77]	10840	1			T2	36		T5	29		T7	12
valid_sources[0x78]	9640	1			T2	48		T5	12		T8	2
valid_sources[0x79]	7903	1			T2	34		T5	5		T7	4
valid_sources[0x7a]	6525	1			T2	18		T5	35		T7	17
valid_sources[0x7b]	6779	1			T2	29		T5	9		T7	9
valid_sources[0x7c]	8172	1			T1	13		T2	17		T5	7
valid_sources[0x7d]	8069	1			T2	41		T5	25		T7	2
valid_sources[0x7e]	7078	1			T2	36		T5	6		T8	1
valid_sources[0x7f]	7758	1			T2	25		T5	17		T7	17
valid_sources[0x80]	6851	1			T1	25		T2	23		T5	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018259

1

T2

4089

T3

430

T5

1252

values[0x0]

all_enables

biggest_size

77436

1

T4

1

T1

289

T2

132

values[0x1]

all_enables

biggest_size

56360

1

T4

2

T1

184

T2

81