Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28225	1			T1	233		T2	17		T3	9
auto[PWRUP]	105	1			T1	2		T8	1		T48	1
auto[ONEST_0]	62	1			T1	2		T48	1		T60	1
auto[ONEST_021]	20	1			T1	1		T48	1		T154	1
auto[ONEST_1]	78	1			T1	1		T15	2		T64	1
auto[ONEST_DONE]	4	1			T212	1		T213	1		T214	1
auto[LP_0]	101	1			T8	1		T15	1		T48	1
auto[LP_021]	19	1			T1	1		T15	1		T48	1
auto[LP_1]	121	1			T1	1		T8	2		T48	2
auto[LP_EVAL]	55	1			T1	1		T8	1		T48	1
auto[LP_SLP]	452	1			T1	6		T8	5		T15	4
auto[LP_PWRUP]	24	1			T60	1		T154	1		T196	1
auto[NP_0]	141	1			T1	2		T8	4		T15	1
auto[NP_021]	26	1			T154	1		T215	1		T203	1
auto[NP_1]	155	1			T1	1		T8	1		T15	3
auto[NP_EVAL]	37	1			T1	1		T8	1		T48	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T15

1

T213

1

T216

1

min

27744

1

T1

227

T2

17

T3

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27753	1			T1	227		T2	17		T3	9
pow[0x1]	9	1			T48	1		T60	1		T203	1
pow[0x2]	15	1			T60	2		T64	1		T212	1
pow[0x3]	32	1			T8	1		T48	2		T60	1
pow[0x4]	63	1			T1	2		T15	2		T48	1
pow[0x5]	124	1			T1	2		T8	1		T60	2
pow[0x6]	231	1			T1	4		T8	1		T15	1
pow[0x7]	449	1			T1	3		T8	5		T15	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

180

1

T1

2

T8

1

T15

1

min

27352

1

T1

218

T2

17

T3

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27352	1			T1	218		T2	17		T3	9
pow[0x6]	1	1			T217	1		-	-		-	-
pow[0x8]	4	1			T196	1		T172	1		T218	1
pow[0x9]	6	1			T219	1		T220	1		T217	1
pow[0xa]	14	1			T48	1		T60	1		T154	2
pow[0xb]	25	1			T48	1		T64	1		T154	2
pow[0xc]	65	1			T1	2		T8	1		T48	1
pow[0xd]	133	1			T1	1		T8	2		T15	1
pow[0xe]	272	1			T1	5		T8	1		T15	3
pow[0xf]	531	1			T1	5		T8	4		T15	4