Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2175	1			T1	22		T8	13		T15	10
auto[PWRUP]	111	1			T8	2		T15	2		T48	2
auto[ONEST_0]	77	1			T15	1		T48	1		T40	1
auto[ONEST_021]	12	1			T1	1		T48	1		T64	1
auto[ONEST_1]	90	1			T1	1		T8	1		T39	1
auto[ONEST_DONE]	3	1			T48	1		T344	1		T345	1
auto[LP_0]	122	1			T1	1		T8	4		T48	1
auto[LP_021]	27	1			T15	1		T48	1		T64	1
auto[LP_1]	122	1			T1	3		T8	3		T212	2
auto[LP_EVAL]	63	1			T8	2		T15	1		T60	1
auto[LP_SLP]	516	1			T1	7		T8	5		T15	3
auto[LP_PWRUP]	27	1			T15	1		T346	2		T347	1
auto[NP_0]	219	1			T1	1		T8	2		T15	2
auto[NP_021]	53	1			T1	1		T15	1		T48	1
auto[NP_1]	218	1			T1	3		T39	3		T48	1
auto[NP_EVAL]	31	1			T48	1		T40	1		T64	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T15

1

T219

1

T348

1

min

1925

1

T1

8

T8

9

T15

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1933	1			T1	8		T8	9		T15	5
pow[0x1]	15	1			T40	1		T349	1		T177	1
pow[0x2]	14	1			T8	1		T154	1		T26	1
pow[0x3]	31	1			T212	1		T61	1		T350	1
pow[0x4]	72	1			T1	2		T8	1		T15	1
pow[0x5]	116	1			T1	1		T8	1		T15	1
pow[0x6]	237	1			T1	5		T8	1		T15	2
pow[0x7]	460	1			T1	7		T8	7		T15	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

184

1

T1

5

T8

2

T15

2

min

1349

1

T1

4

T8

1

T15

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1354	1			T1	4		T8	1		T15	2
pow[0x1]	16	1			T40	1		T18	3		T19	3
pow[0x2]	28	1			T39	1		T40	1		T55	1
pow[0x3]	37	1			T39	1		T41	1		T16	2
pow[0x4]	62	1			T39	4		T40	3		T41	1
pow[0x6]	1	1			T345	1		-	-		-	-
pow[0x7]	3	1			T351	1		T352	1		T310	1
pow[0x8]	4	1			T213	1		T217	1		T353	1
pow[0x9]	7	1			T64	1		T16	1		T26	1
pow[0xa]	20	1			T1	1		T48	1		T60	1
pow[0xb]	36	1			T8	1		T15	1		T48	1
pow[0xc]	68	1			T1	1		T15	1		T48	1
pow[0xd]	144	1			T1	3		T8	5		T48	3
pow[0xe]	320	1			T1	6		T8	2		T15	2
pow[0xf]	524	1			T1	5		T8	5		T15	1