Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T8,T9

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T2,T7,T12
1	0	Covered	T2,T7,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T2,T7,T12
1	0	Covered	T2,T7,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T12,T13
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T13
0	1	Covered	T2,T12,T13
1	0	Covered	T2,T12,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T13
1	0	Covered	T2,T6,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T13
1	0	Covered	T1,T2,T7
1	1	Covered	T4,T1,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T7,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T12
0	1	Covered	T2,T7,T12
1	0	Covered	T2,T7,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T2,T7,T57
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T57
0	1	Covered	T2,T7,T57
1	0	Covered	T2,T7,T57

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T2,T12,T13
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T13
0	1	Covered	T2,T12,T13
1	0	Covered	T2,T12,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T12
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T12
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T6,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T4,T1,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T3,T5,T7
1	1	0	Covered	T3,T5,T7
1	1	1	Covered	T3,T5,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T3,T5,T7
1	1	0	Covered	T3,T5,T7
1	1	1	Covered	T3,T5,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T3,T5,T6
1	1	0	Covered	T3,T5,T6
1	1	1	Covered	T3,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T2,T3,T5
1	1	0	Covered	T2,T3,T5
1	1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T5,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T5,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T3,T5
1	1	Covered	T3,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T2,T5,T8
1	0	Covered	T2,T5,T8

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T57,T59,T39
1	0	Covered	T2,T5,T13

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T57
1	0	Covered	T2,T5,T8
1	1	Covered	T57,T59,T39

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T7,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T7,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T7,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T7,T57

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T12,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T12,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T2,T3,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	33782710	33488395	0	0
gen_filter_match[0].MatchCheck00_A	33782710	10563204	0	0
gen_filter_match[0].MatchCheck01_A	33782710	2416830	0	0
gen_filter_match[0].MatchCheck10_A	33782710	2179471	0	0
gen_filter_match[0].MatchCheck11_A	33782710	18328890	0	0
gen_filter_match[1].MatchCheck00_A	33782710	11007735	0	0
gen_filter_match[1].MatchCheck01_A	33782710	1632228	0	0
gen_filter_match[1].MatchCheck10_A	33782710	1493028	0	0
gen_filter_match[1].MatchCheck11_A	33782710	19355404	0	0
gen_filter_match[2].MatchCheck00_A	33782710	12094545	0	0
gen_filter_match[2].MatchCheck01_A	33782710	674793	0	0
gen_filter_match[2].MatchCheck10_A	33782710	614868	0	0
gen_filter_match[2].MatchCheck11_A	33782710	20104189	0	0
gen_filter_match[3].MatchCheck00_A	33782710	13354623	0	0
gen_filter_match[3].MatchCheck01_A	33782710	374037	0	0
gen_filter_match[3].MatchCheck10_A	33782710	203013	0	0
gen_filter_match[3].MatchCheck11_A	33782710	19556722	0	0
gen_filter_match[4].MatchCheck00_A	33782710	13122053	0	0
gen_filter_match[4].MatchCheck01_A	33782710	4	0	0
gen_filter_match[4].MatchCheck10_A	33782710	98	0	0
gen_filter_match[4].MatchCheck11_A	33782710	20366240	0	0
gen_filter_match[5].MatchCheck00_A	33782710	11656289	0	0
gen_filter_match[5].MatchCheck01_A	33782710	32113	0	0
gen_filter_match[5].MatchCheck10_A	33782710	106	0	0
gen_filter_match[5].MatchCheck11_A	33782710	21799887	0	0
gen_filter_match[6].MatchCheck00_A	33782710	12900046	0	0
gen_filter_match[6].MatchCheck01_A	33782710	301011	0	0
gen_filter_match[6].MatchCheck10_A	33782710	65089	0	0
gen_filter_match[6].MatchCheck11_A	33782710	20222249	0	0
gen_filter_match[7].MatchCheck00_A	33782710	12424580	0	0
gen_filter_match[7].MatchCheck01_A	33782710	171067	0	0
gen_filter_match[7].MatchCheck10_A	33782710	103478	0	0
gen_filter_match[7].MatchCheck11_A	33782710	20789270	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	33488395	0	0
T1	23143	20108	0	0
T2	69920	69867	0	0
T3	34056	33998	0	0
T4	93	5	0	0
T5	119210	119152	0	0
T6	33186	33097	0	0
T7	69867	69812	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	10563204	0	0
T1	23143	20061	0	0
T2	69920	33585	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	3	0	0
T6	33186	33097	0	0
T7	69867	35176	0	0
T8	17716	14658	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	2416830	0	0
T39	32064	0	0	0
T45	40059	0	0	0
T46	35410	0	0	0
T47	79811	0	0	0
T48	26569	0	0	0
T49	64038	0	0	0
T50	33516	0	0	0
T51	740	0	0	0
T59	78763	38964	0	0
T62	0	32617	0	0
T69	0	1	0	0
T144	697	0	0	0
T145	0	33254	0	0
T146	0	33191	0	0
T147	0	33349	0	0
T148	0	100048	0	0
T149	0	36320	0	0
T150	0	33375	0	0
T151	0	33168	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	2179471	0	0
T5	119210	1	0	0
T6	33186	0	0	0
T7	69867	34636	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T65	9247	0	0	0
T69	0	1	0	0
T146	0	32838	0	0
T152	0	33593	0	0
T153	0	32341	0	0
T154	0	32569	0	0
T155	0	1	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	18328890	0	0
T1	23143	47	0	0
T2	69920	36282	0	0
T3	34056	33995	0	0
T5	119210	119148	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	570	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32875	0	0
T13	0	32769	0	0
T14	0	32386	0	0
T15	0	254	0	0
T42	0	65934	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	11007735	0	0
T1	23143	20108	0	0
T2	69920	69867	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	3	0	0
T6	33186	33097	0	0
T7	69867	4	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	1632228	0	0
T30	0	65560	0	0
T39	32064	0	0	0
T45	40059	0	0	0
T46	35410	0	0	0
T47	79811	0	0	0
T48	26569	0	0	0
T57	105125	32052	0	0
T58	32715	0	0	0
T59	78763	0	0	0
T69	0	2	0	0
T122	890	0	0	0
T144	697	0	0	0
T156	0	1	0	0
T157	0	32925	0	0
T158	0	33896	0	0
T159	0	89765	0	0
T160	0	33410	0	0
T161	0	35932	0	0
T162	0	33251	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	1493028	0	0
T5	119210	2	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T40	0	59816	0	0
T52	0	33130	0	0
T57	0	33336	0	0
T65	9247	0	0	0
T69	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	19355404	0	0
T3	34056	33995	0	0
T5	119210	119147	0	0
T6	33186	0	0	0
T7	69867	69808	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32875	0	0
T12	32477	32407	0	0
T13	0	32769	0	0
T14	0	32386	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T57	0	39277	0	0
T58	0	32657	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	12094545	0	0
T1	23143	20108	0	0
T2	69920	69867	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	3	0	0
T6	33186	33097	0	0
T7	69867	35175	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	674793	0	0
T7	69867	1	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	0	0	0
T12	32477	0	0	0
T13	32872	0	0	0
T15	12956	0	0	0
T46	0	35338	0	0
T65	9247	0	0	0
T69	0	2	0	0
T121	805	0	0	0
T164	0	32369	0	0
T165	0	34768	0	0
T166	0	32576	0	0
T167	0	33259	0	0
T168	0	65795	0	0
T169	0	39426	0	0
T170	0	34699	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	614868	0	0
T5	119210	2	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T39	0	29812	0	0
T65	9247	0	0	0
T69	0	2	0	0
T155	0	1	0	0
T163	0	1	0	0
T171	0	37325	0	0
T172	0	1	0	0
T173	0	3	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	20104189	0	0
T3	34056	33995	0	0
T5	119210	119147	0	0
T6	33186	0	0	0
T7	69867	34636	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32875	0	0
T12	32477	32407	0	0
T14	0	32386	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T57	0	39277	0	0
T58	0	32657	0	0
T59	0	38964	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	13354623	0	0
T1	23143	20108	0	0
T2	69920	33585	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	4	0	0
T6	33186	33097	0	0
T7	69867	69812	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	374037	0	0
T64	21519	0	0	0
T92	0	1	0	0
T94	0	32925	0	0
T142	1216	0	0	0
T145	105368	0	0	0
T146	98786	0	0	0
T152	66490	32794	0	0
T156	83096	0	0	0
T174	0	34530	0	0
T175	0	31650	0	0
T176	0	1	0	0
T177	0	580	0	0
T178	0	34534	0	0
T179	0	1	0	0
T180	0	33139	0	0
T181	79583	0	0	0
T182	97283	0	0	0
T183	1175	0	0	0
T184	1087	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	203013	0	0
T5	119210	1	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T16	0	2	0	0
T65	9247	0	0	0
T70	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T172	0	2	0	0
T173	0	3	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	19556722	0	0
T2	69920	36282	0	0
T3	34056	33995	0	0
T5	119210	119147	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32875	0	0
T12	0	32407	0	0
T14	0	32386	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T45	0	39974	0	0
T58	0	32657	0	0
T59	0	39701	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	13122053	0	0
T1	23143	20108	0	0
T2	69920	36286	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	4	0	0
T6	33186	4	0	0
T7	69867	69812	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	4	0	0
T92	107585	1	0	0
T93	121502	0	0	0
T94	98194	0	0	0
T95	41605	0	0	0
T96	33157	0	0	0
T97	34888	0	0	0
T98	38229	0	0	0
T99	69078	0	0	0
T100	82	0	0	0
T176	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	116395	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	98	0	0
T5	119210	1	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T46	0	1	0	0
T62	0	1	0	0
T65	9247	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0
T188	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	20366240	0	0
T2	69920	33581	0	0
T3	34056	33995	0	0
T5	119210	119147	0	0
T6	33186	33093	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32875	0	0
T13	0	32769	0	0
T14	0	32386	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T57	0	104665	0	0
T58	0	32657	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	11656289	0	0
T1	23143	20108	0	0
T2	69920	69867	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	4	0	0
T6	33186	4	0	0
T7	69867	69812	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	32113	0	0
T70	98553	1	0	0
T92	0	1	0	0
T148	100138	0	0	0
T166	0	1	0	0
T179	0	1	0	0
T189	0	1	0	0
T190	0	32095	0	0
T191	0	3	0	0
T192	0	1	0	0
T193	0	3	0	0
T194	0	2	0	0
T195	65722	0	0	0
T196	101044	0	0	0
T197	1206	0	0	0
T198	1137	0	0	0
T199	108460	0	0	0
T200	33277	0	0	0
T201	847	0	0	0
T202	123659	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	106	0	0
T5	119210	2	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T46	0	1	0	0
T57	0	1	0	0
T65	9247	0	0	0
T69	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	21799887	0	0
T3	34056	33995	0	0
T5	119210	119146	0	0
T6	33186	33093	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32874	0	0
T12	32477	0	0	0
T13	0	32769	0	0
T14	0	32386	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T45	0	39974	0	0
T57	0	71328	0	0
T59	0	38964	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	12900046	0	0
T1	23143	20108	0	0
T2	69920	36286	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	4	0	0
T6	33186	33097	0	0
T7	69867	69812	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	301011	0	0
T69	104958	2	0	0
T70	98553	0	0	0
T92	0	1	0	0
T114	0	176780	0	0
T157	99209	0	0	0
T166	0	1	0	0
T176	0	1	0	0
T195	65722	0	0	0
T196	101044	0	0	0
T197	1206	0	0	0
T198	1137	0	0	0
T199	108460	0	0	0
T200	33277	0	0	0
T201	847	0	0	0
T203	0	90979	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	0	33237	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	65089	0	0
T5	119210	2	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T46	0	1	0	0
T57	0	1	0	0
T65	9247	0	0	0
T69	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T163	0	1	0	0
T182	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	20222249	0	0
T2	69920	33581	0	0
T3	34056	33995	0	0
T5	119210	119146	0	0
T6	33186	0	0	0
T7	69867	0	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32874	0	0
T13	0	32769	0	0
T14	0	32385	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T57	0	65387	0	0
T58	0	32657	0	0
T59	0	38964	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	12424580	0	0
T1	23143	20108	0	0
T2	69920	36286	0	0
T3	34056	3	0	0
T4	93	5	0	0
T5	119210	4	0	0
T6	33186	4	0	0
T7	69867	34640	0	0
T8	17716	15228	0	0
T9	956	892	0	0
T10	8600	8509	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	171067	0	0
T70	98553	1	0	0
T94	0	32674	0	0
T148	100138	0	0	0
T164	0	32768	0	0
T176	0	1	0	0
T179	0	1	0	0
T195	65722	0	0	0
T196	101044	0	0	0
T197	1206	0	0	0
T198	1137	0	0	0
T199	108460	0	0	0
T200	33277	0	0	0
T201	847	0	0	0
T202	123659	0	0	0
T204	0	2	0	0
T208	0	1	0	0
T209	0	39290	0	0
T210	0	1	0	0
T211	0	34122	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	103478	0	0
T5	119210	2	0	0
T6	33186	33093	0	0
T7	69867	1	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	1	0	0
T12	32477	0	0	0
T14	0	1	0	0
T15	12956	0	0	0
T57	0	1	0	0
T65	9247	0	0	0
T70	0	1	0	0
T163	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33782710	20789270	0	0
T2	69920	33581	0	0
T3	34056	33995	0	0
T5	119210	119146	0	0
T6	33186	0	0	0
T7	69867	35171	0	0
T8	17716	0	0	0
T9	956	0	0	0
T10	8600	0	0	0
T11	32961	32874	0	0
T12	0	32407	0	0
T14	0	32385	0	0
T15	12956	0	0	0
T42	0	65934	0	0
T57	0	39276	0	0
T59	0	38964	0	0