Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1718	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1826	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1637	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1791	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1897	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1853	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1719	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1768	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1585	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1785	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1778	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1801	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1730	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1886	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1815	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1870	0	0
adc_en_ctl_rd_A	2147483647	1405	0	0
adc_fsm_rst_rd_A	2147483647	1476	0	0
adc_intr_ctl_rd_A	2147483647	1602	0	0
adc_lp_sample_ctl_rd_A	2147483647	1262	0	0
adc_pd_ctl_rd_A	2147483647	1583	0	0
adc_sample_ctl_rd_A	2147483647	1280	0	0
adc_wakeup_ctl_rd_A	2147483647	1380	0	0
intr_enable_rd_A	2147483647	1849	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1718	0	0
T16	186022	25	0	0
T17	0	10	0	0
T18	0	24	0	0
T19	0	16	0	0
T20	0	15	0	0
T21	0	11	0	0
T22	0	20	0	0
T23	0	13	0	0
T24	0	22	0	0
T25	0	25	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T16	186022	17	0	0
T17	0	18	0	0
T18	0	32	0	0
T19	0	23	0	0
T20	0	14	0	0
T21	0	21	0	0
T22	0	5	0	0
T23	0	7	0	0
T24	0	20	0	0
T25	0	21	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1637	0	0
T16	186022	23	0	0
T17	0	17	0	0
T18	0	27	0	0
T19	0	15	0	0
T20	0	13	0	0
T21	0	17	0	0
T22	0	4	0	0
T23	0	25	0	0
T24	0	22	0	0
T25	0	19	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T16	186022	19	0	0
T17	0	34	0	0
T18	0	43	0	0
T19	0	17	0	0
T20	0	7	0	0
T21	0	21	0	0
T22	0	8	0	0
T23	0	15	0	0
T24	0	17	0	0
T25	0	10	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T16	186022	31	0	0
T17	0	6	0	0
T18	0	20	0	0
T19	0	17	0	0
T20	0	10	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	13	0	0
T24	0	30	0	0
T25	0	16	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1853	0	0
T16	186022	15	0	0
T17	0	22	0	0
T18	0	36	0	0
T19	0	18	0	0
T20	0	21	0	0
T21	0	14	0	0
T22	0	8	0	0
T23	0	8	0	0
T24	0	39	0	0
T25	0	16	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T16	186022	25	0	0
T17	0	13	0	0
T18	0	27	0	0
T19	0	23	0	0
T20	0	33	0	0
T21	0	17	0	0
T22	0	13	0	0
T23	0	6	0	0
T24	0	27	0	0
T25	0	14	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1768	0	0
T16	186022	28	0	0
T17	0	16	0	0
T18	0	25	0	0
T19	0	4	0	0
T20	0	16	0	0
T21	0	23	0	0
T22	0	1	0	0
T23	0	6	0	0
T24	0	33	0	0
T25	0	11	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1585	0	0
T16	186022	10	0	0
T17	0	25	0	0
T18	0	11	0	0
T19	0	7	0	0
T20	0	23	0	0
T21	0	11	0	0
T22	0	19	0	0
T23	0	9	0	0
T24	0	15	0	0
T25	0	27	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1785	0	0
T16	186022	18	0	0
T17	0	16	0	0
T18	0	25	0	0
T19	0	28	0	0
T20	0	8	0	0
T21	0	17	0	0
T22	0	23	0	0
T23	0	11	0	0
T24	0	17	0	0
T25	0	13	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1778	0	0
T16	186022	19	0	0
T17	0	12	0	0
T18	0	21	0	0
T19	0	33	0	0
T20	0	13	0	0
T21	0	30	0	0
T22	0	2	0	0
T23	0	12	0	0
T24	0	10	0	0
T25	0	19	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1801	0	0
T16	186022	14	0	0
T17	0	27	0	0
T18	0	17	0	0
T19	0	3	0	0
T20	0	26	0	0
T21	0	17	0	0
T22	0	12	0	0
T23	0	7	0	0
T24	0	22	0	0
T25	0	9	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1730	0	0
T16	186022	28	0	0
T17	0	17	0	0
T18	0	28	0	0
T19	0	16	0	0
T20	0	8	0	0
T21	0	18	0	0
T22	0	17	0	0
T23	0	17	0	0
T24	0	32	0	0
T25	0	20	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1886	0	0
T16	186022	8	0	0
T17	0	12	0	0
T18	0	39	0	0
T19	0	16	0	0
T20	0	27	0	0
T21	0	19	0	0
T22	0	2	0	0
T23	0	9	0	0
T24	0	21	0	0
T25	0	26	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1815	0	0
T16	186022	19	0	0
T17	0	16	0	0
T18	0	41	0	0
T19	0	33	0	0
T20	0	14	0	0
T21	0	12	0	0
T22	0	15	0	0
T23	0	6	0	0
T24	0	25	0	0
T25	0	20	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T16	186022	18	0	0
T17	0	11	0	0
T18	0	26	0	0
T19	0	7	0	0
T20	0	20	0	0
T21	0	15	0	0
T22	0	16	0	0
T23	0	20	0	0
T24	0	18	0	0
T25	0	15	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1405	0	0
T16	186022	17	0	0
T17	0	15	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	25	0	0
T21	0	22	0	0
T22	0	3	0	0
T23	0	17	0	0
T24	0	28	0	0
T25	0	25	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1476	0	0
T16	186022	36	0	0
T17	0	16	0	0
T18	0	42	0	0
T19	0	18	0	0
T20	0	20	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	23	0	0
T24	0	7	0	0
T25	0	16	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602	0	0
T16	186022	22	0	0
T17	0	7	0	0
T18	0	36	0	0
T19	0	14	0	0
T20	0	19	0	0
T21	0	34	0	0
T23	0	13	0	0
T24	0	21	0	0
T25	0	18	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0
T35	0	38	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1262	0	0
T16	186022	18	0	0
T17	0	14	0	0
T18	0	26	0	0
T19	0	22	0	0
T20	0	14	0	0
T21	0	18	0	0
T22	0	6	0	0
T23	0	13	0	0
T24	0	26	0	0
T25	0	12	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1583	0	0
T16	186022	14	0	0
T17	0	17	0	0
T18	0	26	0	0
T19	0	14	0	0
T20	0	8	0	0
T21	0	10	0	0
T22	0	14	0	0
T23	0	20	0	0
T24	0	15	0	0
T25	0	17	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280	0	0
T16	186022	8	0	0
T17	0	19	0	0
T18	0	29	0	0
T19	0	16	0	0
T20	0	18	0	0
T21	0	31	0	0
T22	0	14	0	0
T23	0	4	0	0
T24	0	38	0	0
T25	0	25	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1380	0	0
T16	186022	14	0	0
T17	0	30	0	0
T18	0	33	0	0
T19	0	21	0	0
T20	0	10	0	0
T21	0	19	0	0
T22	0	21	0	0
T23	0	12	0	0
T24	0	23	0	0
T25	0	29	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1849	0	0
T16	186022	42	0	0
T17	0	54	0	0
T18	0	52	0	0
T19	0	12	0	0
T20	0	13	0	0
T21	0	34	0	0
T22	0	22	0	0
T26	264205	0	0	0
T27	33624	0	0	0
T28	162046	0	0	0
T29	213450	0	0	0
T30	157535	0	0	0
T31	309831	0	0	0
T32	220240	0	0	0
T33	407714	0	0	0
T34	984867	0	0	0
T36	0	52	0	0
T37	0	8	0	0
T38	0	21	0	0