Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1227549	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1199200

1

T1

457

T2

937

T3

392

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2124032	1			T1	404		T2	1667		T4	81
values[0x0]	150514	1			T1	212		T2	87		T3	503
values[0x1]	152203	1			T1	209		T2	111		T3	469

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	983675	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1443074

1

T1

526

T2

1139

T3

465

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10502	1			T2	15		T3	3		T5	7
valid_sources[0x01]	8421	1			T2	15		T3	5		T7	3
valid_sources[0x02]	7189	1			T2	10		T3	3		T4	1
valid_sources[0x03]	7322	1			T2	13		T3	6		T5	8
valid_sources[0x04]	7077	1			T2	4		T3	1		T7	11
valid_sources[0x05]	11491	1			T2	4		T3	1		T5	2
valid_sources[0x06]	8264	1			T1	18		T2	11		T3	7
valid_sources[0x07]	7291	1			T2	4		T3	5		T5	11
valid_sources[0x08]	11799	1			T1	13		T2	15		T5	3
valid_sources[0x09]	16952	1			T2	12		T3	1		T5	8
valid_sources[0x0a]	8054	1			T2	5		T3	3		T7	8
valid_sources[0x0b]	12722	1			T2	6		T3	5		T5	5
valid_sources[0x0c]	7489	1			T2	10		T3	6		T5	20
valid_sources[0x0d]	7066	1			T2	13		T3	5		T5	10
valid_sources[0x0e]	15708	1			T2	8		T3	4		T5	3
valid_sources[0x0f]	7213	1			T2	11		T3	2		T5	7
valid_sources[0x10]	8780	1			T2	1		T3	5		T5	5
valid_sources[0x11]	9417	1			T2	3		T3	6		T5	20
valid_sources[0x12]	7218	1			T2	14		T3	2		T6	1
valid_sources[0x13]	7748	1			T2	5		T3	1		T7	5
valid_sources[0x14]	7585	1			T2	8		T3	2		T5	17
valid_sources[0x15]	6939	1			T2	3		T3	4		T4	1
valid_sources[0x16]	11873	1			T2	5		T3	5		T5	19
valid_sources[0x17]	8027	1			T2	6		T3	5		T5	64
valid_sources[0x18]	8370	1			T3	2		T5	19		T7	7
valid_sources[0x19]	7056	1			T2	9		T3	3		T7	7
valid_sources[0x1a]	7091	1			T2	11		T3	5		T5	15
valid_sources[0x1b]	16639	1			T3	8		T6	1		T7	4
valid_sources[0x1c]	7647	1			T2	11		T3	3		T5	43
valid_sources[0x1d]	11927	1			T2	7		T3	4		T7	7
valid_sources[0x1e]	8059	1			T2	8		T3	1		T5	9
valid_sources[0x1f]	7293	1			T2	1		T3	4		T5	26
valid_sources[0x20]	10202	1			T2	2		T3	5		T5	11
valid_sources[0x21]	18968	1			T2	8		T3	4		T7	6
valid_sources[0x22]	7148	1			T2	6		T3	1		T5	11
valid_sources[0x23]	8998	1			T1	162		T2	6		T3	3
valid_sources[0x24]	7179	1			T2	3		T3	7		T7	5
valid_sources[0x25]	8368	1			T2	9		T3	11		T7	6
valid_sources[0x26]	7064	1			T3	5		T7	18		T8	3
valid_sources[0x27]	7069	1			T2	5		T3	2		T5	3
valid_sources[0x28]	7493	1			T2	6		T3	7		T5	8
valid_sources[0x29]	11088	1			T1	13		T2	4		T3	5
valid_sources[0x2a]	11755	1			T2	1		T3	7		T5	17
valid_sources[0x2b]	7093	1			T2	5		T3	1		T5	3
valid_sources[0x2c]	8187	1			T2	3		T3	6		T4	4
valid_sources[0x2d]	8407	1			T2	18		T3	6		T5	6
valid_sources[0x2e]	6917	1			T2	11		T3	1		T5	5
valid_sources[0x2f]	11306	1			T2	3		T5	1		T7	7
valid_sources[0x30]	11314	1			T2	9		T3	1		T5	21
valid_sources[0x31]	12242	1			T2	7		T3	4		T5	14
valid_sources[0x32]	7363	1			T2	3		T7	5		T9	10
valid_sources[0x33]	14246	1			T2	2		T3	4		T5	2
valid_sources[0x34]	6911	1			T2	8		T3	10		T5	2
valid_sources[0x35]	8008	1			T2	5		T3	2		T5	12
valid_sources[0x36]	10586	1			T2	7		T3	1		T5	23
valid_sources[0x37]	7531	1			T2	15		T5	7		T7	13
valid_sources[0x38]	11456	1			T2	14		T3	3		T5	6
valid_sources[0x39]	7158	1			T2	11		T3	4		T5	14
valid_sources[0x3a]	8597	1			T2	12		T3	5		T7	16
valid_sources[0x3b]	8286	1			T1	2		T2	8		T3	8
valid_sources[0x3c]	7189	1			T2	4		T3	5		T5	2
valid_sources[0x3d]	7415	1			T1	4		T2	16		T3	4
valid_sources[0x3e]	6675	1			T2	11		T3	3		T4	1
valid_sources[0x3f]	27227	1			T2	11		T3	2		T5	11
valid_sources[0x40]	6983	1			T2	7		T3	4		T5	12
valid_sources[0x41]	28818	1			T1	13		T2	8		T3	7
valid_sources[0x42]	11736	1			T2	10		T3	5		T4	23
valid_sources[0x43]	7316	1			T2	3		T3	6		T4	3
valid_sources[0x44]	6795	1			T2	3		T3	5		T7	4
valid_sources[0x45]	7387	1			T2	12		T3	5		T7	2
valid_sources[0x46]	8077	1			T2	9		T3	3		T5	19
valid_sources[0x47]	8368	1			T2	13		T3	6		T5	18
valid_sources[0x48]	8363	1			T2	1		T3	4		T5	28
valid_sources[0x49]	7447	1			T2	4		T3	3		T5	9
valid_sources[0x4a]	11612	1			T2	15		T3	5		T5	6
valid_sources[0x4b]	7314	1			T2	9		T3	2		T5	10
valid_sources[0x4c]	11797	1			T2	12		T3	3		T5	8
valid_sources[0x4d]	8997	1			T2	20		T5	11		T7	5
valid_sources[0x4e]	6951	1			T2	6		T3	7		T5	10
valid_sources[0x4f]	6941	1			T1	15		T2	3		T3	5
valid_sources[0x50]	7367	1			T1	15		T2	3		T3	6
valid_sources[0x51]	7514	1			T2	15		T3	1		T4	2
valid_sources[0x52]	9866	1			T2	2		T3	6		T5	5
valid_sources[0x53]	8230	1			T2	5		T3	2		T4	6
valid_sources[0x54]	7401	1			T1	1		T2	10		T3	1
valid_sources[0x55]	7249	1			T2	8		T3	4		T5	11
valid_sources[0x56]	7247	1			T1	5		T2	13		T3	9
valid_sources[0x57]	11963	1			T2	7		T5	4		T7	3
valid_sources[0x58]	7085	1			T2	5		T5	22		T7	10
valid_sources[0x59]	7086	1			T2	2		T3	6		T5	13
valid_sources[0x5a]	12214	1			T2	13		T3	8		T5	22
valid_sources[0x5b]	18564	1			T2	4		T3	4		T5	4
valid_sources[0x5c]	9280	1			T3	6		T5	8		T6	1
valid_sources[0x5d]	7052	1			T3	2		T7	12		T9	11
valid_sources[0x5e]	7626	1			T2	9		T3	4		T5	29
valid_sources[0x5f]	8053	1			T2	2		T3	4		T5	4
valid_sources[0x60]	8249	1			T2	9		T3	4		T7	4
valid_sources[0x61]	8537	1			T2	16		T3	7		T5	8
valid_sources[0x62]	8146	1			T2	3		T3	5		T5	7
valid_sources[0x63]	8089	1			T2	5		T3	6		T7	13
valid_sources[0x64]	6882	1			T2	4		T4	5		T7	6
valid_sources[0x65]	8050	1			T1	1		T2	3		T3	5
valid_sources[0x66]	8774	1			T2	3		T3	5		T5	3
valid_sources[0x67]	7364	1			T2	3		T3	2		T5	12
valid_sources[0x68]	7219	1			T2	4		T3	2		T5	7
valid_sources[0x69]	7135	1			T2	10		T5	4		T7	11
valid_sources[0x6a]	7182	1			T2	4		T3	1		T4	1
valid_sources[0x6b]	7181	1			T3	6		T5	13		T7	17
valid_sources[0x6c]	12688	1			T2	4		T3	5		T5	12
valid_sources[0x6d]	7995	1			T2	7		T3	3		T4	1
valid_sources[0x6e]	7146	1			T2	4		T3	4		T7	18
valid_sources[0x6f]	12040	1			T2	9		T3	7		T5	4
valid_sources[0x70]	6758	1			T2	2		T3	2		T7	10
valid_sources[0x71]	8410	1			T2	2		T3	3		T4	1
valid_sources[0x72]	8048	1			T2	6		T3	3		T7	17
valid_sources[0x73]	7317	1			T2	3		T3	2		T5	15
valid_sources[0x74]	7996	1			T2	7		T3	6		T7	11
valid_sources[0x75]	10147	1			T2	10		T3	2		T5	42
valid_sources[0x76]	14804	1			T3	2		T5	23		T7	12
valid_sources[0x77]	9418	1			T1	15		T2	2		T3	3
valid_sources[0x78]	9369	1			T2	17		T5	12		T6	2
valid_sources[0x79]	9534	1			T2	8		T3	3		T5	21
valid_sources[0x7a]	16448	1			T3	1		T4	5		T5	1
valid_sources[0x7b]	12402	1			T2	4		T3	2		T5	4
valid_sources[0x7c]	10513	1			T2	2		T3	3		T5	73
valid_sources[0x7d]	10630	1			T2	27		T3	2		T5	10
valid_sources[0x7e]	7913	1			T2	5		T3	2		T5	40
valid_sources[0x7f]	7041	1			T2	7		T3	6		T7	7
valid_sources[0x80]	7149	1			T2	16		T3	6		T7	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1057498

1

T1

228

T2

841

T4

34

values[0x0]

all_enables

biggest_size

81935

1

T1

133

T2

50

T3

241

values[0x1]

all_enables

biggest_size

59767

1

T1

96

T2

46

T3

151