Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
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Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
91.11 91.11 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_fsm_reset_cg_inst 91.11 1 100 1 64 64



Group Instance : adc_ctrl_fsm_reset_cg_inst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.11 1 100 1 64 64



Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 45 4 41 91.11


Variables for Group Instance adc_ctrl_fsm_reset_cg_inst
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
fsm_state_cp 17 1 16 94.12 100 1 1 0
lp_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
lp_sample_cnt_pow_cp 8 0 8 100.00 100 1 1 0
np_sample_cnt_min_max_cp 2 0 2 100.00 100 1 1 0
np_sample_cnt_pow_cp 16 3 13 81.25 100 1 1 0


Summary for Variable fsm_state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 17 1 16 94.12


Automatically Generated Bins for fsm_state_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[NP_DONE] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[PWRDN] 30560 1 T1 29 T2 19 T3 267
auto[PWRUP] 101 1 T5 4 T8 2 T55 2
auto[ONEST_0] 72 1 T3 3 T5 1 T8 1
auto[ONEST_021] 17 1 T5 1 T207 1 T28 1
auto[ONEST_1] 99 1 T3 1 T5 4 T8 2
auto[ONEST_DONE] 3 1 T5 2 T208 1 - -
auto[LP_0] 130 1 T3 3 T5 3 T8 3
auto[LP_021] 34 1 T66 1 T209 1 T210 1
auto[LP_1] 153 1 T3 1 T12 1 T173 5
auto[LP_EVAL] 80 1 T5 1 T8 2 T12 2
auto[LP_SLP] 482 1 T1 1 T3 1 T5 9
auto[LP_PWRUP] 39 1 T3 1 T56 1 T173 1
auto[NP_0] 172 1 T3 3 T5 2 T8 5
auto[NP_021] 42 1 T1 1 T8 1 T55 1
auto[NP_1] 177 1 T1 1 T3 2 T5 3
auto[NP_EVAL] 41 1 T3 2 T5 1 T8 1


Summary for Variable lp_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for lp_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 5 1 T66 1 T211 1 T114 1
min 30033 1 T1 28 T2 19 T3 253


Summary for Variable lp_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for lp_sample_cnt_pow_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 30040 1 T1 28 T2 19 T3 253
pow[0x1] 10 1 T8 1 T212 1 T213 1
pow[0x2] 15 1 T8 1 T56 1 T207 1
pow[0x3] 36 1 T3 1 T56 1 T61 1
pow[0x4] 63 1 T3 1 T5 2 T55 1
pow[0x5] 141 1 T3 1 T5 1 T8 3
pow[0x6] 255 1 T3 5 T5 6 T8 2
pow[0x7] 557 1 T1 1 T3 9 T5 9


Summary for Variable np_sample_cnt_min_max_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for np_sample_cnt_min_max_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
max 210 1 T3 3 T5 7 T8 1
min 29585 1 T1 27 T2 19 T3 251


Summary for Variable np_sample_cnt_pow_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 16 3 13 81.25


User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   STATUS   
pow[0x1] 0 1 1
pow[0x3] 0 1 1
pow[0x7] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
pow[0x0] 29585 1 T1 27 T2 19 T3 251
pow[0x2] 1 1 T41 1 - - - -
pow[0x4] 1 1 T3 1 - - - -
pow[0x5] 1 1 T41 1 - - - -
pow[0x6] 2 1 T3 1 T214 1 - -
pow[0x8] 9 1 T69 1 T207 2 T68 1
pow[0x9] 3 1 T207 1 T215 1 T216 1
pow[0xa] 17 1 T5 1 T69 1 T159 1
pow[0xb] 37 1 T3 1 T5 1 T8 1
pow[0xc] 69 1 T5 3 T55 1 T56 1
pow[0xd] 148 1 T3 1 T5 2 T8 4
pow[0xe] 275 1 T1 1 T3 3 T5 7
pow[0xf] 573 1 T1 1 T3 7 T5 9