Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2348	1			T1	17		T3	24		T5	39
auto[PWRUP]	161	1			T3	3		T5	6		T8	3
auto[ONEST_0]	96	1			T5	3		T8	1		T12	2
auto[ONEST_021]	26	1			T55	1		T69	1		T52	1
auto[ONEST_1]	108	1			T1	1		T5	1		T8	1
auto[ONEST_DONE]	2	1			T5	1		T23	1		-	-
auto[LP_0]	120	1			T5	4		T12	3		T55	2
auto[LP_021]	24	1			T1	1		T67	1		T207	3
auto[LP_1]	142	1			T3	4		T5	2		T8	1
auto[LP_EVAL]	60	1			T1	2		T5	2		T8	2
auto[LP_SLP]	539	1			T1	2		T3	6		T5	16
auto[LP_PWRUP]	39	1			T5	1		T12	1		T56	1
auto[NP_0]	220	1			T1	3		T5	4		T8	1
auto[NP_021]	47	1			T1	1		T146	1		T48	1
auto[NP_1]	252	1			T1	1		T3	1		T5	11
auto[NP_EVAL]	29	1			T12	1		T50	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T286

1

T213

1

T345

1

min

2019

1

T1

16

T3

8

T5

38

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2033	1			T1	16		T3	8		T5	38
pow[0x1]	14	1			T8	1		T52	1		T37	1
pow[0x2]	23	1			T12	1		T69	1		T159	1
pow[0x3]	31	1			T1	1		T12	1		T69	1
pow[0x4]	71	1			T1	2		T3	1		T8	1
pow[0x5]	126	1			T3	3		T5	5		T12	1
pow[0x6]	271	1			T3	9		T5	9		T12	2
pow[0x7]	559	1			T1	7		T3	3		T5	17

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

208

1

T3

4

T5

7

T8

4

min

1391

1

T1

13

T5

22

T8

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1399	1			T1	13		T5	23		T8	2
pow[0x1]	13	1			T61	1		T104	2		T253	5
pow[0x2]	37	1			T50	1		T16	4		T17	3
pow[0x3]	59	1			T1	2		T5	1		T12	4
pow[0x4]	41	1			T5	1		T47	1		T48	6
pow[0x5]	2	1			T69	1		T346	1		-	-
pow[0x8]	5	1			T5	1		T41	1		T347	1
pow[0x9]	10	1			T3	1		T348	1		T215	1
pow[0xa]	19	1			T1	1		T3	1		T60	1
pow[0xb]	39	1			T3	1		T5	3		T49	2
pow[0xc]	88	1			T3	2		T5	3		T173	2
pow[0xd]	157	1			T1	2		T3	2		T5	6
pow[0xe]	274	1			T1	1		T3	2		T5	4
pow[0xf]	599	1			T1	3		T3	7		T5	12