Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2251	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2224	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2337	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2143	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2136	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2168	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1949	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2251	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1995	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2159	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2251	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2259	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2161	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2397	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1986	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1963	0	0
adc_en_ctl_rd_A	2147483647	1898	0	0
adc_fsm_rst_rd_A	2147483647	1867	0	0
adc_intr_ctl_rd_A	2147483647	2233	0	0
adc_lp_sample_ctl_rd_A	2147483647	1723	0	0
adc_pd_ctl_rd_A	2147483647	2092	0	0
adc_sample_ctl_rd_A	2147483647	1822	0	0
adc_wakeup_ctl_rd_A	2147483647	1861	0	0
intr_enable_rd_A	2147483647	2297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T16	488759	20	0	0
T17	0	33	0	0
T18	0	49	0	0
T19	0	11	0	0
T20	0	32	0	0
T21	0	15	0	0
T22	0	10	0	0
T23	0	32	0	0
T24	0	26	0	0
T25	0	1	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2224	0	0
T16	488759	14	0	0
T17	0	33	0	0
T18	0	37	0	0
T19	0	10	0	0
T20	0	30	0	0
T21	0	15	0	0
T22	0	3	0	0
T23	0	21	0	0
T24	0	30	0	0
T25	0	11	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2337	0	0
T16	488759	9	0	0
T17	0	48	0	0
T18	0	41	0	0
T19	0	21	0	0
T20	0	37	0	0
T21	0	13	0	0
T22	0	10	0	0
T23	0	21	0	0
T24	0	34	0	0
T25	0	12	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2143	0	0
T16	488759	17	0	0
T17	0	20	0	0
T18	0	27	0	0
T19	0	18	0	0
T20	0	40	0	0
T21	0	19	0	0
T22	0	23	0	0
T23	0	25	0	0
T24	0	25	0	0
T25	0	17	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T16	488759	13	0	0
T17	0	33	0	0
T18	0	22	0	0
T19	0	6	0	0
T20	0	35	0	0
T21	0	19	0	0
T22	0	17	0	0
T23	0	10	0	0
T24	0	16	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0
T35	0	54	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2168	0	0
T16	488759	18	0	0
T17	0	38	0	0
T18	0	41	0	0
T19	0	6	0	0
T20	0	28	0	0
T21	0	22	0	0
T22	0	19	0	0
T23	0	31	0	0
T24	0	19	0	0
T25	0	5	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1949	0	0
T16	488759	1	0	0
T17	0	27	0	0
T18	0	38	0	0
T19	0	8	0	0
T20	0	34	0	0
T21	0	20	0	0
T22	0	6	0	0
T23	0	26	0	0
T24	0	28	0	0
T25	0	3	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T16	488759	11	0	0
T17	0	11	0	0
T18	0	42	0	0
T19	0	5	0	0
T20	0	15	0	0
T21	0	16	0	0
T22	0	13	0	0
T23	0	16	0	0
T24	0	49	0	0
T25	0	8	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T16	488759	32	0	0
T17	0	23	0	0
T18	0	27	0	0
T19	0	3	0	0
T20	0	24	0	0
T21	0	13	0	0
T22	0	25	0	0
T23	0	33	0	0
T24	0	31	0	0
T25	0	4	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T16	488759	12	0	0
T17	0	46	0	0
T18	0	53	0	0
T19	0	4	0	0
T20	0	56	0	0
T21	0	11	0	0
T22	0	15	0	0
T23	0	18	0	0
T24	0	37	0	0
T25	0	4	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2251	0	0
T16	488759	9	0	0
T17	0	20	0	0
T18	0	41	0	0
T19	0	11	0	0
T20	0	30	0	0
T21	0	12	0	0
T22	0	16	0	0
T23	0	39	0	0
T24	0	36	0	0
T25	0	16	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2259	0	0
T16	488759	12	0	0
T17	0	26	0	0
T18	0	43	0	0
T19	0	1	0	0
T20	0	54	0	0
T21	0	26	0	0
T22	0	16	0	0
T23	0	26	0	0
T24	0	35	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0
T35	0	35	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T16	488759	11	0	0
T17	0	24	0	0
T18	0	28	0	0
T19	0	25	0	0
T20	0	29	0	0
T21	0	20	0	0
T22	0	21	0	0
T23	0	33	0	0
T24	0	27	0	0
T25	0	8	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T16	488759	15	0	0
T17	0	22	0	0
T18	0	32	0	0
T19	0	20	0	0
T20	0	29	0	0
T21	0	16	0	0
T22	0	13	0	0
T23	0	12	0	0
T24	0	24	0	0
T25	0	13	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1986	0	0
T16	488759	24	0	0
T17	0	29	0	0
T18	0	26	0	0
T19	0	4	0	0
T20	0	40	0	0
T21	0	16	0	0
T22	0	12	0	0
T23	0	27	0	0
T24	0	44	0	0
T25	0	10	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1963	0	0
T16	488759	7	0	0
T17	0	21	0	0
T18	0	40	0	0
T19	0	8	0	0
T20	0	30	0	0
T21	0	18	0	0
T22	0	4	0	0
T23	0	15	0	0
T24	0	40	0	0
T25	0	26	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1898	0	0
T16	488759	8	0	0
T17	0	34	0	0
T18	0	38	0	0
T19	0	6	0	0
T20	0	37	0	0
T21	0	21	0	0
T22	0	26	0	0
T23	0	31	0	0
T24	0	12	0	0
T25	0	12	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1867	0	0
T16	488759	16	0	0
T17	0	50	0	0
T18	0	38	0	0
T19	0	10	0	0
T20	0	26	0	0
T21	0	20	0	0
T22	0	12	0	0
T23	0	38	0	0
T24	0	24	0	0
T25	0	11	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2233	0	0
T17	182483	26	0	0
T18	0	43	0	0
T19	0	15	0	0
T20	0	37	0	0
T21	0	20	0	0
T22	0	8	0	0
T23	0	23	0	0
T24	0	33	0	0
T25	0	8	0	0
T35	0	35	0	0
T36	511874	0	0	0
T37	499158	0	0	0
T38	783694	0	0	0
T39	188529	0	0	0
T40	939767	0	0	0
T41	370622	0	0	0
T42	76622	0	0	0
T43	812608	0	0	0
T44	506151	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1723	0	0
T16	488759	23	0	0
T17	0	33	0	0
T18	0	35	0	0
T19	0	4	0	0
T20	0	26	0	0
T21	0	18	0	0
T22	0	21	0	0
T23	0	29	0	0
T24	0	24	0	0
T25	0	19	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T16	488759	2	0	0
T17	0	17	0	0
T18	0	24	0	0
T19	0	4	0	0
T20	0	32	0	0
T21	0	16	0	0
T22	0	24	0	0
T23	0	39	0	0
T24	0	18	0	0
T25	0	12	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1822	0	0
T16	488759	1	0	0
T17	0	31	0	0
T18	0	25	0	0
T19	0	5	0	0
T20	0	14	0	0
T21	0	25	0	0
T22	0	20	0	0
T23	0	40	0	0
T24	0	25	0	0
T25	0	13	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1861	0	0
T16	488759	6	0	0
T17	0	30	0	0
T18	0	34	0	0
T19	0	12	0	0
T20	0	31	0	0
T21	0	17	0	0
T22	0	20	0	0
T23	0	44	0	0
T24	0	13	0	0
T25	0	3	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2297	0	0
T16	488759	18	0	0
T17	0	26	0	0
T18	0	60	0	0
T19	0	35	0	0
T20	0	87	0	0
T21	0	27	0	0
T22	0	4	0	0
T23	0	73	0	0
T26	974286	0	0	0
T27	38815	0	0	0
T28	509708	0	0	0
T29	118817	0	0	0
T30	161733	0	0	0
T31	768930	0	0	0
T32	161455	0	0	0
T33	505335	0	0	0
T34	52773	0	0	0
T45	0	4	0	0
T46	0	11	0	0