Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1162175	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1132765

1

T1

922

T2

6316

T3

511

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2005505	1			T1	1696		T2	11975		T3	844
values[0x0]	144193	1			T1	99		T2	378		T3	57
values[0x1]	145242	1			T1	104		T2	357		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	931588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1363352

1

T1

1115

T2

7591

T3

588

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9857	1			T1	27		T2	41		T5	17
valid_sources[0x01]	6937	1			T1	8		T2	45		T5	91
valid_sources[0x02]	7351	1			T1	4		T2	43		T5	42
valid_sources[0x03]	6353	1			T1	3		T2	46		T6	2
valid_sources[0x04]	6557	1			T1	14		T2	59		T6	5
valid_sources[0x05]	11716	1			T1	8		T2	52		T5	17
valid_sources[0x06]	10977	1			T1	9		T2	47		T6	6
valid_sources[0x07]	7592	1			T2	61		T5	25		T6	3
valid_sources[0x08]	6826	1			T1	26		T2	39		T14	1
valid_sources[0x09]	6661	1			T1	8		T2	60		T5	20
valid_sources[0x0a]	6863	1			T1	12		T2	72		T6	2
valid_sources[0x0b]	6481	1			T1	2		T2	61		T5	49
valid_sources[0x0c]	11264	1			T1	8		T2	49		T6	10
valid_sources[0x0d]	19616	1			T1	3		T2	47		T5	110
valid_sources[0x0e]	9573	1			T1	7		T2	40		T5	62
valid_sources[0x0f]	7308	1			T1	19		T2	48		T6	8
valid_sources[0x10]	6371	1			T1	12		T2	48		T6	4
valid_sources[0x11]	6885	1			T1	5		T2	40		T5	80
valid_sources[0x12]	6607	1			T1	7		T2	53		T6	14
valid_sources[0x13]	15243	1			T1	11		T2	47		T5	30
valid_sources[0x14]	7579	1			T2	50		T6	5		T8	18
valid_sources[0x15]	21092	1			T1	5		T2	46		T5	20
valid_sources[0x16]	6373	1			T1	3		T2	44		T5	62
valid_sources[0x17]	7807	1			T1	5		T2	53		T5	10
valid_sources[0x18]	9768	1			T1	4		T2	53		T5	47
valid_sources[0x19]	7790	1			T1	2		T2	55		T5	42
valid_sources[0x1a]	7976	1			T1	9		T2	50		T6	8
valid_sources[0x1b]	9059	1			T1	4		T2	62		T5	10
valid_sources[0x1c]	6127	1			T1	4		T2	55		T6	4
valid_sources[0x1d]	7476	1			T2	49		T5	92		T6	4
valid_sources[0x1e]	6695	1			T2	50		T6	5		T10	7
valid_sources[0x1f]	8972	1			T1	5		T2	47		T6	8
valid_sources[0x20]	6632	1			T1	11		T2	54		T5	101
valid_sources[0x21]	11456	1			T1	3		T2	56		T6	27
valid_sources[0x22]	6576	1			T2	61		T6	3		T7	1
valid_sources[0x23]	7127	1			T1	16		T2	40		T5	17
valid_sources[0x24]	6437	1			T1	5		T2	55		T14	3
valid_sources[0x25]	19158	1			T1	2		T2	47		T6	4
valid_sources[0x26]	10602	1			T2	35		T5	55		T14	1
valid_sources[0x27]	6228	1			T1	3		T2	54		T5	44
valid_sources[0x28]	7523	1			T1	2		T2	65		T5	26
valid_sources[0x29]	6871	1			T1	6		T2	46		T5	12
valid_sources[0x2a]	6756	1			T1	12		T2	50		T6	8
valid_sources[0x2b]	6737	1			T1	2		T2	51		T5	9
valid_sources[0x2c]	7343	1			T1	10		T2	41		T3	1
valid_sources[0x2d]	10185	1			T1	14		T2	40		T6	12
valid_sources[0x2e]	8586	1			T1	17		T2	54		T3	952
valid_sources[0x2f]	10901	1			T1	15		T2	51		T6	5
valid_sources[0x30]	9227	1			T1	2		T2	45		T5	17
valid_sources[0x31]	6821	1			T1	3		T2	51		T5	6
valid_sources[0x32]	6186	1			T1	9		T2	43		T6	7
valid_sources[0x33]	6303	1			T2	53		T5	21		T6	5
valid_sources[0x34]	13084	1			T1	3		T2	46		T6	10
valid_sources[0x35]	6859	1			T1	6		T2	54		T5	4
valid_sources[0x36]	6821	1			T1	14		T2	43		T5	10
valid_sources[0x37]	7056	1			T2	53		T6	8		T10	8
valid_sources[0x38]	9269	1			T2	45		T6	6		T10	4
valid_sources[0x39]	6898	1			T1	9		T2	54		T6	6
valid_sources[0x3a]	6600	1			T1	8		T2	61		T6	13
valid_sources[0x3b]	12497	1			T1	7		T2	46		T6	6
valid_sources[0x3c]	8925	1			T1	13		T2	62		T5	22
valid_sources[0x3d]	6811	1			T1	6		T2	53		T5	10
valid_sources[0x3e]	6696	1			T2	55		T6	11		T10	9
valid_sources[0x3f]	11710	1			T1	5		T2	45		T14	1
valid_sources[0x40]	6688	1			T2	58		T14	5		T6	7
valid_sources[0x41]	8189	1			T1	1		T2	52		T5	18
valid_sources[0x42]	6600	1			T1	15		T2	52		T6	5
valid_sources[0x43]	6330	1			T1	10		T2	36		T6	7
valid_sources[0x44]	10178	1			T1	7		T2	43		T5	1
valid_sources[0x45]	8381	1			T1	7		T2	51		T5	39
valid_sources[0x46]	7276	1			T1	6		T2	63		T6	6
valid_sources[0x47]	15341	1			T1	13		T2	58		T6	12
valid_sources[0x48]	6692	1			T1	4		T2	51		T6	9
valid_sources[0x49]	11231	1			T2	53		T5	20		T6	6
valid_sources[0x4a]	10223	1			T1	25		T2	56		T5	35
valid_sources[0x4b]	8605	1			T1	9		T2	58		T5	67
valid_sources[0x4c]	6846	1			T1	6		T2	64		T5	35
valid_sources[0x4d]	10858	1			T1	2		T2	43		T6	9
valid_sources[0x4e]	6825	1			T1	4		T2	34		T5	17
valid_sources[0x4f]	6883	1			T1	4		T2	40		T6	6
valid_sources[0x50]	6871	1			T1	5		T2	43		T6	3
valid_sources[0x51]	11464	1			T2	46		T6	8		T10	20
valid_sources[0x52]	11709	1			T1	7		T2	63		T5	22
valid_sources[0x53]	6404	1			T1	15		T2	49		T6	7
valid_sources[0x54]	6993	1			T1	8		T2	36		T5	62
valid_sources[0x55]	6521	1			T1	9		T2	54		T6	11
valid_sources[0x56]	6720	1			T1	8		T2	53		T5	25
valid_sources[0x57]	6465	1			T2	65		T5	39		T6	8
valid_sources[0x58]	7958	1			T1	8		T2	41		T5	111
valid_sources[0x59]	6792	1			T1	1		T2	57		T5	11
valid_sources[0x5a]	9369	1			T1	6		T2	48		T5	17
valid_sources[0x5b]	6225	1			T1	2		T2	48		T6	9
valid_sources[0x5c]	6601	1			T1	10		T2	42		T6	16
valid_sources[0x5d]	7956	1			T1	3		T2	59		T5	29
valid_sources[0x5e]	7704	1			T1	3		T2	43		T5	4
valid_sources[0x5f]	7799	1			T1	8		T2	51		T5	44
valid_sources[0x60]	12390	1			T1	19		T2	43		T6	11
valid_sources[0x61]	11106	1			T1	8		T2	49		T6	8
valid_sources[0x62]	6749	1			T1	1		T2	47		T6	3
valid_sources[0x63]	17245	1			T1	29		T2	52		T6	5
valid_sources[0x64]	7104	1			T1	7		T2	43		T5	29
valid_sources[0x65]	6322	1			T1	26		T2	35		T5	29
valid_sources[0x66]	8892	1			T1	11		T2	55		T6	22
valid_sources[0x67]	9303	1			T1	4		T2	56		T6	6
valid_sources[0x68]	7624	1			T1	11		T2	49		T5	22
valid_sources[0x69]	18924	1			T1	10		T2	47		T5	19
valid_sources[0x6a]	10876	1			T1	15		T2	56		T5	109
valid_sources[0x6b]	7798	1			T1	4		T2	54		T6	7
valid_sources[0x6c]	6464	1			T2	51		T6	5		T10	7
valid_sources[0x6d]	16928	1			T1	12		T2	38		T6	1
valid_sources[0x6e]	6885	1			T2	30		T5	14		T6	8
valid_sources[0x6f]	6419	1			T1	5		T2	49		T6	3
valid_sources[0x70]	10944	1			T1	9		T2	51		T6	21
valid_sources[0x71]	7957	1			T1	6		T2	55		T5	57
valid_sources[0x72]	7342	1			T1	2		T2	52		T5	7
valid_sources[0x73]	6617	1			T1	15		T2	62		T5	29
valid_sources[0x74]	6821	1			T1	5		T2	52		T5	3
valid_sources[0x75]	6442	1			T1	5		T2	48		T6	11
valid_sources[0x76]	7368	1			T1	2		T2	45		T5	72
valid_sources[0x77]	6337	1			T1	7		T2	47		T5	16
valid_sources[0x78]	6417	1			T1	4		T2	43		T6	2
valid_sources[0x79]	13465	1			T1	5		T2	46		T6	4
valid_sources[0x7a]	6758	1			T1	7		T2	46		T5	7
valid_sources[0x7b]	10640	1			T1	2		T2	47		T6	6
valid_sources[0x7c]	10701	1			T1	8		T2	47		T5	23
valid_sources[0x7d]	8135	1			T1	5		T2	55		T6	4
valid_sources[0x7e]	9038	1			T1	1		T2	46		T5	4
valid_sources[0x7f]	15459	1			T1	9		T2	46		T5	137
valid_sources[0x80]	6747	1			T1	5		T2	51		T5	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

998945

1

T1

827

T2

6021

T3

458

values[0x0]

all_enables

biggest_size

78157

1

T1

54

T2

186

T3

31

values[0x1]

all_enables

biggest_size

55663

1

T1

41

T2

109

T3

22