Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30793	1			T1	11		T2	18		T3	8
auto[PWRUP]	115	1			T8	1		T28	1		T32	3
auto[ONEST_0]	91	1			T8	1		T28	3		T32	1
auto[ONEST_021]	19	1			T8	2		T28	1		T39	1
auto[ONEST_1]	88	1			T8	3		T28	1		T49	2
auto[ONEST_DONE]	2	1			T8	1		T226	1		-	-
auto[LP_0]	139	1			T8	2		T9	3		T28	1
auto[LP_021]	29	1			T32	1		T227	1		T228	1
auto[LP_1]	123	1			T8	2		T9	1		T28	3
auto[LP_EVAL]	83	1			T9	1		T15	2		T32	1
auto[LP_SLP]	557	1			T8	7		T9	3		T28	10
auto[LP_PWRUP]	26	1			T9	1		T15	1		T28	1
auto[NP_0]	169	1			T8	3		T9	1		T28	4
auto[NP_021]	26	1			T8	2		T9	1		T49	1
auto[NP_1]	177	1			T8	3		T9	2		T15	1
auto[NP_EVAL]	39	1			T8	1		T32	2		T227	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T84

1

T229

1

T230

1

min

30267

1

T1

11

T2

18

T3

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30274	1			T1	11		T2	18		T3	8
pow[0x1]	8	1			T51	1		T229	2		T230	2
pow[0x2]	14	1			T49	1		T231	1		T51	1
pow[0x3]	39	1			T32	1		T40	1		T232	1
pow[0x4]	71	1			T8	1		T9	2		T28	2
pow[0x5]	127	1			T8	3		T9	1		T15	2
pow[0x6]	265	1			T8	8		T9	3		T28	3
pow[0x7]	546	1			T8	9		T9	4		T15	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

208

1

T8

1

T9

2

T15

1

min

29741

1

T1

11

T2

18

T3

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29741	1			T1	11		T2	18		T3	8
pow[0x3]	1	1			T233	1		-	-		-	-
pow[0x4]	1	1			T234	1		-	-		-	-
pow[0x5]	3	1			T235	1		T236	1		T237	1
pow[0x7]	4	1			T238	1		T237	1		T239	1
pow[0x8]	12	1			T233	2		T229	1		T240	2
pow[0x9]	11	1			T9	1		T49	1		T232	1
pow[0xa]	22	1			T9	1		T15	1		T28	1
pow[0xb]	41	1			T15	1		T28	1		T32	1
pow[0xc]	74	1			T8	1		T9	1		T28	2
pow[0xd]	165	1			T8	6		T28	1		T49	2
pow[0xe]	310	1			T8	2		T9	8		T28	3
pow[0xf]	633	1			T8	6		T9	5		T15	2