Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2321	1			T8	24		T9	13		T15	22
auto[PWRUP]	153	1			T8	4		T9	1		T28	1
auto[ONEST_0]	76	1			T9	1		T28	2		T49	3
auto[ONEST_021]	17	1			T8	1		T232	1		T359	1
auto[ONEST_1]	80	1			T8	1		T15	1		T28	1
auto[ONEST_DONE]	6	1			T231	1		T19	1		T230	1
auto[LP_0]	122	1			T8	1		T9	1		T28	2
auto[LP_021]	41	1			T9	1		T28	1		T32	1
auto[LP_1]	182	1			T8	3		T9	2		T28	3
auto[LP_EVAL]	58	1			T28	2		T32	1		T39	2
auto[LP_SLP]	566	1			T8	7		T9	2		T28	13
auto[LP_PWRUP]	32	1			T28	1		T227	1		T40	1
auto[NP_0]	238	1			T8	1		T9	3		T15	5
auto[NP_021]	45	1			T8	1		T9	1		T49	2
auto[NP_1]	221	1			T8	2		T9	1		T15	4
auto[NP_EVAL]	29	1			T39	1		T40	2		T231	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T28

1

T227

1

T360

1

min

1976

1

T8

12

T9

5

T15

26

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1987	1			T8	12		T9	5		T15	26
pow[0x1]	17	1			T28	1		T252	1		T293	1
pow[0x2]	16	1			T84	1		T360	1		T361	1
pow[0x3]	31	1			T9	2		T32	2		T49	1
pow[0x4]	71	1			T8	1		T9	2		T28	2
pow[0x5]	132	1			T8	4		T28	1		T32	1
pow[0x6]	271	1			T8	4		T9	2		T15	1
pow[0x7]	562	1			T8	9		T9	5		T15	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

187

1

T8

2

T9

3

T15

1

min

1320

1

T8

6

T9

3

T15

18

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1322	1			T8	6		T9	3		T15	19
pow[0x1]	7	1			T20	4		T299	1		T362	2
pow[0x2]	26	1			T15	1		T39	2		T41	1
pow[0x3]	51	1			T15	4		T40	2		T43	2
pow[0x4]	56	1			T15	2		T40	4		T16	1
pow[0x5]	3	1			T8	1		T229	1		T363	1
pow[0x6]	3	1			T84	1		T364	1		T365	1
pow[0x7]	1	1			T84	1		-	-		-	-
pow[0x8]	5	1			T349	1		T236	1		T366	1
pow[0x9]	12	1			T8	1		T229	1		T361	1
pow[0xa]	16	1			T8	1		T39	1		T227	1
pow[0xb]	44	1			T8	1		T28	1		T32	1
pow[0xc]	93	1			T8	1		T28	2		T32	2
pow[0xd]	158	1			T8	1		T9	1		T28	3
pow[0xe]	327	1			T8	5		T28	7		T32	6
pow[0xf]	627	1			T8	6		T9	4		T15	1