Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1999	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1994	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2115	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2163	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2192	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2148	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2182	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2054	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2151	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1897	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2079	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2094	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2127	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2092	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1959	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2001	0	0
adc_en_ctl_rd_A	2147483647	1662	0	0
adc_fsm_rst_rd_A	2147483647	1351	0	0
adc_intr_ctl_rd_A	2147483647	1831	0	0
adc_lp_sample_ctl_rd_A	2147483647	1470	0	0
adc_pd_ctl_rd_A	2147483647	1953	0	0
adc_sample_ctl_rd_A	2147483647	1378	0	0
adc_wakeup_ctl_rd_A	2147483647	1664	0	0
intr_enable_rd_A	2147483647	2058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1999	0	0
T15	681631	49	0	0
T16	0	11	0	0
T17	0	43	0	0
T18	0	10	0	0
T19	0	34	0	0
T20	0	15	0	0
T21	0	16	0	0
T22	0	18	0	0
T23	0	38	0	0
T24	0	9	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1994	0	0
T15	681631	26	0	0
T16	0	16	0	0
T17	0	38	0	0
T18	0	2	0	0
T19	0	37	0	0
T20	0	13	0	0
T21	0	20	0	0
T22	0	25	0	0
T23	0	39	0	0
T24	0	10	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T15	681631	33	0	0
T16	0	20	0	0
T17	0	39	0	0
T18	0	5	0	0
T19	0	37	0	0
T20	0	20	0	0
T21	0	21	0	0
T22	0	27	0	0
T23	0	38	0	0
T24	0	27	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2163	0	0
T15	681631	43	0	0
T16	0	4	0	0
T17	0	43	0	0
T18	0	10	0	0
T19	0	39	0	0
T20	0	20	0	0
T21	0	21	0	0
T22	0	23	0	0
T23	0	33	0	0
T24	0	7	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T15	681631	18	0	0
T16	0	18	0	0
T17	0	39	0	0
T18	0	11	0	0
T19	0	31	0	0
T20	0	29	0	0
T21	0	14	0	0
T22	0	16	0	0
T23	0	22	0	0
T24	0	26	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2148	0	0
T15	681631	31	0	0
T16	0	23	0	0
T17	0	25	0	0
T18	0	13	0	0
T19	0	42	0	0
T20	0	21	0	0
T21	0	18	0	0
T22	0	15	0	0
T23	0	41	0	0
T24	0	7	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2182	0	0
T15	681631	31	0	0
T16	0	14	0	0
T17	0	23	0	0
T18	0	17	0	0
T19	0	34	0	0
T20	0	26	0	0
T21	0	15	0	0
T22	0	24	0	0
T23	0	50	0	0
T24	0	13	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2054	0	0
T15	681631	44	0	0
T16	0	19	0	0
T17	0	60	0	0
T18	0	7	0	0
T19	0	20	0	0
T20	0	12	0	0
T21	0	21	0	0
T22	0	18	0	0
T23	0	39	0	0
T24	0	29	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2151	0	0
T15	681631	17	0	0
T16	0	18	0	0
T17	0	32	0	0
T18	0	13	0	0
T19	0	29	0	0
T20	0	46	0	0
T21	0	29	0	0
T22	0	17	0	0
T23	0	27	0	0
T24	0	14	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1897	0	0
T15	681631	21	0	0
T16	0	8	0	0
T17	0	23	0	0
T18	0	9	0	0
T19	0	22	0	0
T20	0	27	0	0
T21	0	26	0	0
T22	0	27	0	0
T23	0	36	0	0
T24	0	18	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2079	0	0
T15	681631	22	0	0
T16	0	7	0	0
T17	0	30	0	0
T18	0	24	0	0
T19	0	40	0	0
T20	0	6	0	0
T21	0	15	0	0
T22	0	19	0	0
T23	0	28	0	0
T24	0	19	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2094	0	0
T15	681631	31	0	0
T16	0	14	0	0
T17	0	38	0	0
T18	0	8	0	0
T19	0	25	0	0
T20	0	8	0	0
T21	0	12	0	0
T22	0	31	0	0
T23	0	48	0	0
T24	0	15	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2127	0	0
T15	681631	22	0	0
T16	0	15	0	0
T17	0	48	0	0
T18	0	14	0	0
T19	0	40	0	0
T20	0	9	0	0
T21	0	39	0	0
T22	0	29	0	0
T23	0	31	0	0
T24	0	4	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T15	681631	28	0	0
T16	0	9	0	0
T17	0	32	0	0
T18	0	8	0	0
T19	0	33	0	0
T20	0	17	0	0
T21	0	20	0	0
T22	0	19	0	0
T23	0	25	0	0
T24	0	20	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1959	0	0
T15	681631	21	0	0
T16	0	10	0	0
T17	0	21	0	0
T18	0	7	0	0
T19	0	34	0	0
T20	0	12	0	0
T21	0	20	0	0
T22	0	13	0	0
T23	0	31	0	0
T24	0	13	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2001	0	0
T15	681631	31	0	0
T16	0	21	0	0
T17	0	18	0	0
T18	0	8	0	0
T19	0	33	0	0
T20	0	22	0	0
T21	0	15	0	0
T22	0	15	0	0
T23	0	38	0	0
T24	0	2	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T15	681631	20	0	0
T16	0	4	0	0
T17	0	22	0	0
T18	0	7	0	0
T19	0	43	0	0
T20	0	1	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	0	45	0	0
T24	0	10	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1351	0	0
T15	681631	27	0	0
T16	0	6	0	0
T17	0	21	0	0
T18	0	14	0	0
T19	0	28	0	0
T20	0	17	0	0
T21	0	31	0	0
T22	0	7	0	0
T23	0	26	0	0
T24	0	27	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1831	0	0
T15	681631	9	0	0
T16	0	18	0	0
T17	0	21	0	0
T18	0	22	0	0
T19	0	23	0	0
T20	0	20	0	0
T21	0	25	0	0
T22	0	23	0	0
T23	0	57	0	0
T24	0	16	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1470	0	0
T15	681631	29	0	0
T16	0	20	0	0
T17	0	24	0	0
T18	0	20	0	0
T19	0	49	0	0
T20	0	13	0	0
T21	0	32	0	0
T22	0	17	0	0
T23	0	26	0	0
T24	0	21	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1953	0	0
T15	681631	28	0	0
T16	0	15	0	0
T17	0	37	0	0
T18	0	17	0	0
T19	0	39	0	0
T20	0	21	0	0
T21	0	19	0	0
T22	0	25	0	0
T23	0	33	0	0
T24	0	13	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378	0	0
T15	681631	23	0	0
T16	0	11	0	0
T17	0	34	0	0
T18	0	25	0	0
T19	0	32	0	0
T20	0	30	0	0
T21	0	18	0	0
T22	0	23	0	0
T23	0	45	0	0
T24	0	6	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1664	0	0
T15	681631	24	0	0
T16	0	17	0	0
T17	0	37	0	0
T18	0	11	0	0
T19	0	40	0	0
T21	0	7	0	0
T22	0	8	0	0
T23	0	45	0	0
T24	0	21	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0
T34	0	38	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2058	0	0
T15	681631	95	0	0
T16	0	19	0	0
T17	0	42	0	0
T18	0	36	0	0
T19	0	111	0	0
T20	0	28	0	0
T25	411908	0	0	0
T26	133121	0	0	0
T27	915002	0	0	0
T28	296334	0	0	0
T29	161014	0	0	0
T30	476586	0	0	0
T31	27375	0	0	0
T32	253901	0	0	0
T33	115943	0	0	0
T35	0	10	0	0
T36	0	56	0	0
T37	0	15	0	0
T38	0	24	0	0