Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1226404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1204912

1

T4

2

T1

2690

T2

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2138261	1			T4	1		T1	4989		T5	4132
values[0x0]	146568	1			T4	2		T1	281		T2	36
values[0x1]	146487	1			T1	278		T2	25		T3	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	983013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1448303

1

T4

2

T1

3232

T2

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11157	1			T1	6		T6	18		T8	9
valid_sources[0x01]	12130	1			T1	26		T6	14		T8	11
valid_sources[0x02]	7118	1			T1	31		T6	20		T7	17
valid_sources[0x03]	8016	1			T1	4		T5	29		T6	21
valid_sources[0x04]	13956	1			T1	10		T5	2		T6	15
valid_sources[0x05]	7227	1			T1	13		T5	9		T6	15
valid_sources[0x06]	12405	1			T1	19		T6	16		T8	5
valid_sources[0x07]	7087	1			T1	12		T6	16		T8	9
valid_sources[0x08]	6871	1			T1	12		T6	25		T8	3
valid_sources[0x09]	7649	1			T1	5		T5	5		T6	10
valid_sources[0x0a]	11137	1			T1	7		T6	14		T8	4
valid_sources[0x0b]	11592	1			T4	1		T1	9		T5	8
valid_sources[0x0c]	9607	1			T1	24		T6	17		T8	9
valid_sources[0x0d]	7392	1			T1	58		T5	3		T6	16
valid_sources[0x0e]	10002	1			T1	5		T5	29		T6	18
valid_sources[0x0f]	10770	1			T1	71		T5	3		T6	24
valid_sources[0x10]	7415	1			T1	3		T6	20		T7	32
valid_sources[0x11]	7256	1			T1	4		T6	23		T8	11
valid_sources[0x12]	7111	1			T4	1		T1	10		T6	16
valid_sources[0x13]	7262	1			T1	2		T3	1		T5	25
valid_sources[0x14]	8532	1			T1	13		T5	8		T6	19
valid_sources[0x15]	11641	1			T1	42		T6	11		T8	3
valid_sources[0x16]	12671	1			T1	62		T3	3		T6	16
valid_sources[0x17]	8404	1			T1	16		T6	15		T8	12
valid_sources[0x18]	15582	1			T1	5		T6	4264		T8	6
valid_sources[0x19]	11773	1			T1	28		T3	1		T6	19
valid_sources[0x1a]	8035	1			T1	9		T6	15		T8	9
valid_sources[0x1b]	7891	1			T1	13		T5	24		T6	13
valid_sources[0x1c]	9607	1			T1	6		T6	15		T8	4
valid_sources[0x1d]	7945	1			T1	11		T6	10		T8	4
valid_sources[0x1e]	7889	1			T1	149		T6	12		T8	10
valid_sources[0x1f]	6799	1			T1	27		T5	1		T6	23
valid_sources[0x20]	9230	1			T1	19		T6	12		T8	4
valid_sources[0x21]	8118	1			T1	51		T5	12		T6	25
valid_sources[0x22]	11294	1			T1	77		T5	50		T6	19
valid_sources[0x23]	11806	1			T1	19		T5	103		T6	15
valid_sources[0x24]	7213	1			T1	51		T5	13		T6	16
valid_sources[0x25]	6974	1			T1	66		T5	49		T6	15
valid_sources[0x26]	11417	1			T1	13		T5	9		T6	21
valid_sources[0x27]	8040	1			T1	14		T5	6		T6	12
valid_sources[0x28]	11408	1			T1	11		T6	22		T8	11
valid_sources[0x29]	7302	1			T1	2		T6	20		T8	11
valid_sources[0x2a]	13028	1			T1	17		T5	8		T6	13
valid_sources[0x2b]	7207	1			T1	69		T5	4		T6	15
valid_sources[0x2c]	11032	1			T1	7		T5	17		T6	12
valid_sources[0x2d]	8626	1			T4	1		T1	115		T5	167
valid_sources[0x2e]	11105	1			T1	47		T6	9		T8	6
valid_sources[0x2f]	7083	1			T1	11		T5	22		T6	20
valid_sources[0x30]	11134	1			T1	11		T5	3		T6	24
valid_sources[0x31]	6897	1			T1	19		T6	22		T8	8
valid_sources[0x32]	12498	1			T1	9		T6	19		T8	10
valid_sources[0x33]	14083	1			T1	3		T6	9		T8	4
valid_sources[0x34]	10983	1			T1	4		T5	26		T6	9
valid_sources[0x35]	12891	1			T1	8		T6	18		T8	7
valid_sources[0x36]	11317	1			T1	9		T6	18		T8	4
valid_sources[0x37]	8147	1			T1	36		T6	18		T8	12
valid_sources[0x38]	11775	1			T1	31		T6	14		T8	6
valid_sources[0x39]	13036	1			T1	4		T5	1		T6	17
valid_sources[0x3a]	15444	1			T1	5		T6	15		T8	3
valid_sources[0x3b]	6840	1			T1	18		T5	2		T6	22
valid_sources[0x3c]	7516	1			T1	25		T5	91		T6	19
valid_sources[0x3d]	9953	1			T1	23		T5	54		T6	13
valid_sources[0x3e]	8690	1			T1	6		T5	32		T6	25
valid_sources[0x3f]	14490	1			T1	4		T5	23		T6	20
valid_sources[0x40]	7506	1			T1	3		T6	13		T8	2
valid_sources[0x41]	7015	1			T1	70		T5	35		T6	16
valid_sources[0x42]	20569	1			T1	18		T6	13		T8	8
valid_sources[0x43]	20390	1			T1	53		T5	15		T6	13
valid_sources[0x44]	7510	1			T1	10		T5	28		T6	28
valid_sources[0x45]	8449	1			T1	14		T5	32		T6	19
valid_sources[0x46]	7313	1			T1	6		T3	1		T5	29
valid_sources[0x47]	10099	1			T1	14		T5	62		T6	16
valid_sources[0x48]	15715	1			T1	40		T3	4		T6	18
valid_sources[0x49]	7813	1			T1	7		T6	9		T7	20
valid_sources[0x4a]	9346	1			T1	24		T6	22		T8	4
valid_sources[0x4b]	12242	1			T1	74		T6	19		T8	3
valid_sources[0x4c]	10550	1			T1	116		T5	72		T6	22
valid_sources[0x4d]	7002	1			T1	9		T6	16		T8	10
valid_sources[0x4e]	9659	1			T1	10		T5	9		T6	11
valid_sources[0x4f]	8099	1			T1	36		T6	21		T8	7
valid_sources[0x50]	6977	1			T1	156		T6	17		T8	8
valid_sources[0x51]	8249	1			T1	4		T5	41		T6	20
valid_sources[0x52]	11718	1			T1	73		T6	12		T8	9
valid_sources[0x53]	14574	1			T1	25		T5	60		T6	15
valid_sources[0x54]	6875	1			T1	18		T6	14		T8	6
valid_sources[0x55]	14618	1			T1	18		T6	21		T8	2
valid_sources[0x56]	6869	1			T1	11		T6	27		T7	14
valid_sources[0x57]	7317	1			T1	7		T6	17		T7	23
valid_sources[0x58]	7050	1			T1	36		T6	15		T8	6
valid_sources[0x59]	7300	1			T1	9		T5	17		T6	24
valid_sources[0x5a]	11495	1			T1	14		T5	11		T6	16
valid_sources[0x5b]	6949	1			T1	5		T5	1		T6	19
valid_sources[0x5c]	8042	1			T1	3		T6	13		T8	6
valid_sources[0x5d]	7947	1			T1	11		T5	20		T6	15
valid_sources[0x5e]	8113	1			T1	17		T5	41		T6	24
valid_sources[0x5f]	19072	1			T1	8		T5	1		T6	21
valid_sources[0x60]	11950	1			T1	11		T5	163		T6	15
valid_sources[0x61]	7125	1			T1	56		T5	7		T6	19
valid_sources[0x62]	16208	1			T1	69		T5	24		T6	18
valid_sources[0x63]	6888	1			T1	9		T5	17		T6	18
valid_sources[0x64]	8978	1			T1	6		T6	23		T8	5
valid_sources[0x65]	17203	1			T1	16		T6	15		T8	10
valid_sources[0x66]	7268	1			T1	27		T6	13		T7	6
valid_sources[0x67]	14250	1			T1	24		T5	39		T6	19
valid_sources[0x68]	7141	1			T1	3		T6	18		T8	9
valid_sources[0x69]	7889	1			T1	9		T5	22		T6	22
valid_sources[0x6a]	11692	1			T1	24		T5	1		T6	20
valid_sources[0x6b]	6880	1			T1	29		T5	43		T6	18
valid_sources[0x6c]	8297	1			T1	25		T3	1		T5	6
valid_sources[0x6d]	7824	1			T1	6		T6	17		T8	5
valid_sources[0x6e]	7470	1			T1	7		T6	24		T8	6
valid_sources[0x6f]	7046	1			T1	14		T6	23		T8	4
valid_sources[0x70]	14044	1			T1	6		T5	42		T6	17
valid_sources[0x71]	16557	1			T1	5		T6	4341		T8	3
valid_sources[0x72]	7663	1			T1	17		T6	13		T8	9
valid_sources[0x73]	7146	1			T1	19		T5	17		T6	22
valid_sources[0x74]	14203	1			T1	9		T6	13		T8	5
valid_sources[0x75]	8046	1			T1	70		T6	19		T8	7
valid_sources[0x76]	13131	1			T1	35		T5	18		T6	18
valid_sources[0x77]	8321	1			T1	13		T5	137		T6	19
valid_sources[0x78]	7085	1			T1	10		T5	27		T6	19
valid_sources[0x79]	7340	1			T1	19		T5	54		T6	23
valid_sources[0x7a]	6988	1			T1	9		T5	24		T6	9
valid_sources[0x7b]	7258	1			T1	7		T5	2		T6	18
valid_sources[0x7c]	8358	1			T1	7		T5	1		T6	17
valid_sources[0x7d]	11542	1			T1	15		T6	10		T8	3
valid_sources[0x7e]	7469	1			T1	76		T3	4		T6	18
valid_sources[0x7f]	7392	1			T1	15		T5	135		T6	19
valid_sources[0x80]	11114	1			T1	11		T5	86		T6	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1067489

1

T4

1

T1

2465

T5

2093

values[0x0]

all_enables

biggest_size

80012

1

T4

1

T1

141

T2

22

values[0x1]

all_enables

biggest_size

57411

1

T1

84

T2

11

T3

6