Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28506	1			T1	15		T5	5		T6	19
auto[PWRUP]	88	1			T10	2		T54	2		T55	2
auto[ONEST_0]	73	1			T10	1		T53	1		T54	1
auto[ONEST_021]	20	1			T10	1		T53	1		T55	1
auto[ONEST_1]	58	1			T53	2		T54	1		T51	1
auto[ONEST_DONE]	2	1			T195	1		T196	1		-	-
auto[LP_0]	113	1			T10	2		T53	3		T54	1
auto[LP_021]	25	1			T7	1		T53	1		T34	1
auto[LP_1]	116	1			T10	1		T53	3		T54	2
auto[LP_EVAL]	65	1			T10	3		T55	1		T51	1
auto[LP_SLP]	469	1			T7	5		T10	4		T53	10
auto[LP_PWRUP]	23	1			T53	1		T55	1		T197	2
auto[NP_0]	138	1			T7	3		T10	4		T55	1
auto[NP_021]	36	1			T55	2		T198	1		T199	1
auto[NP_1]	126	1			T10	1		T54	2		T55	2
auto[NP_EVAL]	35	1			T7	1		T55	1		T51	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T200

1

T19

1

T201

1

min

27964

1

T1

15

T5

5

T6

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27975	1			T1	15		T5	5		T6	19
pow[0x1]	7	1			T53	1		T202	1		T203	1
pow[0x2]	17	1			T54	1		T55	1		T51	1
pow[0x3]	25	1			T51	1		T195	1		T198	1
pow[0x4]	46	1			T53	2		T54	1		T55	2
pow[0x5]	145	1			T7	2		T53	5		T54	2
pow[0x6]	247	1			T7	3		T10	4		T53	4
pow[0x7]	484	1			T7	4		T10	10		T53	10

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

181

1

T7

4

T10

1

T53

7

min

27501

1

T1

15

T5

5

T6

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27501	1			T1	15		T5	5		T6	19
pow[0x4]	1	1			T204	1		-	-		-	-
pow[0x6]	1	1			T201	1		-	-		-	-
pow[0x7]	3	1			T10	1		T205	1		T206	1
pow[0x8]	3	1			T207	1		T208	1		T209	1
pow[0x9]	13	1			T199	1		T201	1		T210	1
pow[0xa]	18	1			T10	1		T53	1		T201	1
pow[0xb]	38	1			T10	1		T53	1		T54	1
pow[0xc]	77	1			T7	1		T10	2		T53	1
pow[0xd]	115	1			T53	1		T54	1		T55	4
pow[0xe]	273	1			T7	1		T10	3		T53	7
pow[0xf]	564	1			T7	5		T10	9		T53	7