Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2208	1			T4	20		T5	5		T7	15
auto[PWRUP]	122	1			T7	2		T10	3		T53	1
auto[ONEST_0]	85	1			T10	1		T55	1		T51	2
auto[ONEST_021]	18	1			T55	1		T51	1		T18	1
auto[ONEST_1]	101	1			T7	1		T54	2		T55	3
auto[ONEST_DONE]	2	1			T342	1		T56	1		-	-
auto[LP_0]	115	1			T7	2		T10	1		T54	4
auto[LP_021]	27	1			T53	1		T51	1		T34	2
auto[LP_1]	132	1			T7	1		T10	2		T53	2
auto[LP_EVAL]	67	1			T7	1		T53	1		T54	1
auto[LP_SLP]	517	1			T7	3		T10	2		T53	6
auto[LP_PWRUP]	29	1			T54	1		T55	1		T51	1
auto[NP_0]	199	1			T7	1		T10	1		T53	1
auto[NP_021]	55	1			T10	2		T54	1		T55	1
auto[NP_1]	179	1			T7	1		T53	1		T54	1
auto[NP_EVAL]	43	1			T53	1		T54	1		T55	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T207

1

T202

1

T208

1

min

1923

1

T4

20

T5

5

T7

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1944	1			T4	20		T5	5		T7	5
pow[0x1]	14	1			T343	1		T210	1		T344	1
pow[0x2]	12	1			T197	1		T45	1		T207	1
pow[0x3]	36	1			T34	1		T44	1		T195	1
pow[0x4]	67	1			T54	1		T55	1		T52	1
pow[0x5]	135	1			T53	3		T54	1		T55	3
pow[0x6]	255	1			T7	6		T53	4		T54	2
pow[0x7]	481	1			T7	9		T10	5		T53	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T7

1

T10

1

T53

3

min

1342

1

T4

20

T5

5

T7

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1347	1			T4	20		T5	5		T7	1
pow[0x1]	10	1			T49	1		T345	1		T346	1
pow[0x2]	31	1			T16	1		T17	4		T44	1
pow[0x3]	37	1			T16	1		T18	4		T46	4
pow[0x4]	53	1			T16	1		T44	1		T19	2
pow[0x5]	1	1			T204	1		-	-		-	-
pow[0x6]	2	1			T347	1		T284	1		-	-
pow[0x7]	3	1			T348	1		T349	1		T196	1
pow[0x8]	6	1			T350	1		T256	1		T351	1
pow[0x9]	9	1			T53	1		T34	1		T200	1
pow[0xa]	17	1			T54	1		T199	2		T197	1
pow[0xb]	37	1			T51	2		T198	1		T19	1
pow[0xc]	79	1			T10	2		T51	1		T34	1
pow[0xd]	130	1			T7	2		T10	1		T53	1
pow[0xe]	261	1			T7	7		T10	3		T53	3
pow[0xf]	577	1			T7	5		T10	4		T53	7