Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1281263	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1250791

1

T1

488

T2

4150

T3

2071

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2237860	1			T1	847		T2	8022		T3	4012
values[0x0]	146918	1			T1	55		T2	227		T3	117
values[0x1]	147276	1			T1	38		T2	245		T3	107

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1026194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1505860

1

T1

569

T2

4992

T3

2480

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7167	1			T1	4		T2	14		T3	18
valid_sources[0x01]	7101	1			T1	1		T2	19		T3	26
valid_sources[0x02]	8713	1			T1	2		T2	16		T3	15
valid_sources[0x03]	7320	1			T1	6		T2	23		T3	9
valid_sources[0x04]	13977	1			T1	1		T2	12		T3	24
valid_sources[0x05]	7274	1			T1	4		T2	10		T3	20
valid_sources[0x06]	7342	1			T1	5		T2	12		T3	12
valid_sources[0x07]	7449	1			T1	4		T2	14		T3	33
valid_sources[0x08]	13656	1			T1	11		T2	30		T3	21
valid_sources[0x09]	11706	1			T2	19		T3	12		T5	11
valid_sources[0x0a]	7728	1			T1	2		T2	8		T3	13
valid_sources[0x0b]	12569	1			T1	1		T2	12		T3	6
valid_sources[0x0c]	7474	1			T1	4		T2	15		T3	23
valid_sources[0x0d]	20429	1			T2	17		T3	15		T5	5
valid_sources[0x0e]	10387	1			T1	5		T2	36		T3	5
valid_sources[0x0f]	8534	1			T1	4		T2	17		T3	14
valid_sources[0x10]	12127	1			T1	8		T2	23		T3	15
valid_sources[0x11]	7375	1			T1	7		T2	26		T3	19
valid_sources[0x12]	11710	1			T1	6		T2	8		T3	12
valid_sources[0x13]	9855	1			T1	2		T2	8		T3	12
valid_sources[0x14]	7666	1			T1	8		T2	36		T3	22
valid_sources[0x15]	7593	1			T1	7		T2	14		T3	16
valid_sources[0x16]	10612	1			T1	6		T2	12		T3	26
valid_sources[0x17]	8233	1			T1	3		T2	26		T3	26
valid_sources[0x18]	7896	1			T1	4		T2	12		T3	14
valid_sources[0x19]	7957	1			T1	4		T2	25		T3	16
valid_sources[0x1a]	7631	1			T1	2		T2	8		T3	26
valid_sources[0x1b]	7242	1			T2	18		T3	13		T5	1
valid_sources[0x1c]	12146	1			T1	4		T2	15		T3	13
valid_sources[0x1d]	21444	1			T1	2		T2	24		T3	19
valid_sources[0x1e]	14433	1			T1	3		T2	19		T3	15
valid_sources[0x1f]	7397	1			T1	2		T2	22		T3	13
valid_sources[0x20]	11421	1			T1	6		T2	15		T3	21
valid_sources[0x21]	16011	1			T1	4		T2	20		T3	16
valid_sources[0x22]	7814	1			T1	2		T2	15		T3	12
valid_sources[0x23]	8047	1			T1	4		T2	24		T3	18
valid_sources[0x24]	11624	1			T1	3		T2	19		T3	17
valid_sources[0x25]	7822	1			T1	7		T2	24		T3	12
valid_sources[0x26]	14321	1			T1	13		T2	14		T3	12
valid_sources[0x27]	7050	1			T1	2		T2	14		T3	18
valid_sources[0x28]	7704	1			T1	5		T2	9		T3	24
valid_sources[0x29]	6906	1			T2	18		T3	18		T5	3
valid_sources[0x2a]	8258	1			T1	3		T2	18		T3	20
valid_sources[0x2b]	7918	1			T1	6		T2	10		T3	22
valid_sources[0x2c]	7284	1			T1	8		T2	21		T3	13
valid_sources[0x2d]	13317	1			T1	2		T2	14		T3	18
valid_sources[0x2e]	8348	1			T1	3		T2	29		T3	11
valid_sources[0x2f]	7007	1			T1	3		T2	24		T3	10
valid_sources[0x30]	12313	1			T1	1		T2	13		T3	16
valid_sources[0x31]	7649	1			T1	7		T2	15		T3	15
valid_sources[0x32]	11281	1			T1	1		T2	18		T3	23
valid_sources[0x33]	7926	1			T1	6		T2	23		T3	22
valid_sources[0x34]	14366	1			T1	3		T2	21		T3	13
valid_sources[0x35]	7136	1			T1	2		T2	9		T3	20
valid_sources[0x36]	14490	1			T2	17		T3	20		T5	5
valid_sources[0x37]	13734	1			T1	6		T2	17		T3	14
valid_sources[0x38]	7632	1			T1	6		T2	21		T3	23
valid_sources[0x39]	9918	1			T2	20		T3	15		T5	4
valid_sources[0x3a]	11567	1			T1	7		T2	25		T3	15
valid_sources[0x3b]	7389	1			T1	7		T2	17		T3	11
valid_sources[0x3c]	7132	1			T1	4		T2	21		T3	28
valid_sources[0x3d]	11546	1			T1	4		T2	5		T3	8
valid_sources[0x3e]	7371	1			T1	9		T2	8		T3	15
valid_sources[0x3f]	11187	1			T1	7		T2	10		T3	15
valid_sources[0x40]	11753	1			T1	1		T2	18		T3	22
valid_sources[0x41]	11348	1			T1	4		T2	10		T3	11
valid_sources[0x42]	7539	1			T2	23		T3	16		T5	4
valid_sources[0x43]	7171	1			T2	11		T3	9		T5	1
valid_sources[0x44]	7232	1			T1	3		T2	14		T3	14
valid_sources[0x45]	11651	1			T2	16		T3	11		T4	1
valid_sources[0x46]	11394	1			T1	6		T2	14		T3	15
valid_sources[0x47]	23176	1			T1	10		T2	4157		T3	18
valid_sources[0x48]	12688	1			T1	7		T2	16		T3	23
valid_sources[0x49]	8193	1			T1	2		T2	12		T3	10
valid_sources[0x4a]	7449	1			T2	13		T3	17		T5	5
valid_sources[0x4b]	11685	1			T1	1		T2	21		T3	26
valid_sources[0x4c]	12546	1			T1	3		T2	24		T3	15
valid_sources[0x4d]	7664	1			T1	3		T2	22		T3	9
valid_sources[0x4e]	7198	1			T1	4		T2	23		T3	18
valid_sources[0x4f]	7214	1			T1	2		T2	42		T3	14
valid_sources[0x50]	9414	1			T1	1		T2	15		T3	5
valid_sources[0x51]	7378	1			T1	5		T2	13		T3	16
valid_sources[0x52]	16254	1			T1	3		T2	21		T3	15
valid_sources[0x53]	7209	1			T1	5		T2	8		T3	13
valid_sources[0x54]	12504	1			T1	2		T2	18		T3	13
valid_sources[0x55]	16243	1			T2	9		T3	26		T5	4
valid_sources[0x56]	7281	1			T1	4		T2	19		T3	18
valid_sources[0x57]	7520	1			T1	5		T2	6		T3	9
valid_sources[0x58]	7559	1			T1	3		T2	21		T3	19
valid_sources[0x59]	7296	1			T1	6		T2	16		T3	22
valid_sources[0x5a]	12246	1			T1	1		T2	28		T3	17
valid_sources[0x5b]	8242	1			T1	3		T2	15		T3	17
valid_sources[0x5c]	10005	1			T1	4		T2	11		T3	19
valid_sources[0x5d]	12943	1			T1	5		T2	13		T3	15
valid_sources[0x5e]	12588	1			T2	24		T3	25		T5	3
valid_sources[0x5f]	7854	1			T1	3		T2	13		T3	20
valid_sources[0x60]	7261	1			T1	3		T2	30		T3	28
valid_sources[0x61]	7045	1			T1	7		T2	16		T3	20
valid_sources[0x62]	12152	1			T1	5		T2	7		T3	15
valid_sources[0x63]	7231	1			T1	1		T2	8		T3	21
valid_sources[0x64]	13328	1			T1	1		T2	14		T3	23
valid_sources[0x65]	7718	1			T1	2		T2	11		T3	26
valid_sources[0x66]	11989	1			T1	1		T2	13		T3	14
valid_sources[0x67]	7556	1			T1	3		T2	10		T3	18
valid_sources[0x68]	7584	1			T1	3		T2	6		T3	16
valid_sources[0x69]	7431	1			T1	1		T2	22		T3	9
valid_sources[0x6a]	7166	1			T1	4		T2	14		T3	29
valid_sources[0x6b]	7420	1			T1	2		T2	16		T3	8
valid_sources[0x6c]	11231	1			T1	2		T2	18		T3	19
valid_sources[0x6d]	13713	1			T1	6		T2	25		T3	16
valid_sources[0x6e]	7692	1			T1	6		T2	12		T3	17
valid_sources[0x6f]	17653	1			T1	9		T2	5		T3	25
valid_sources[0x70]	7467	1			T1	3		T2	14		T3	11
valid_sources[0x71]	11220	1			T1	1		T2	29		T3	11
valid_sources[0x72]	13915	1			T2	18		T3	11		T5	6
valid_sources[0x73]	7573	1			T1	7		T2	9		T3	21
valid_sources[0x74]	7300	1			T1	6		T2	24		T3	12
valid_sources[0x75]	9409	1			T1	3		T2	5		T3	26
valid_sources[0x76]	8412	1			T1	2		T2	8		T3	19
valid_sources[0x77]	11951	1			T2	31		T3	11		T5	1
valid_sources[0x78]	7354	1			T1	6		T2	23		T3	18
valid_sources[0x79]	8343	1			T2	18		T3	12		T5	3
valid_sources[0x7a]	7502	1			T1	2		T2	13		T3	12
valid_sources[0x7b]	25438	1			T1	1		T2	14		T3	11
valid_sources[0x7c]	7609	1			T1	3		T2	34		T3	13
valid_sources[0x7d]	12067	1			T1	7		T2	19		T3	16
valid_sources[0x7e]	7950	1			T1	1		T2	23		T3	17
valid_sources[0x7f]	8123	1			T2	7		T3	9		T5	3
valid_sources[0x80]	14757	1			T1	1		T2	7		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1114433

1

T1

444

T2

3981

T3

1985

values[0x0]

all_enables

biggest_size

79775

1

T1

32

T2

104

T3

58

values[0x1]

all_enables

biggest_size

56583

1

T1

12

T2

65

T3

28