Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28912	1			T1	6		T2	14		T3	7
auto[PWRUP]	114	1			T50	2		T51	1		T52	1
auto[ONEST_0]	65	1			T50	1		T177	1		T178	2
auto[ONEST_021]	22	1			T179	1		T180	1		T181	1
auto[ONEST_1]	83	1			T50	1		T45	1		T51	1
auto[ONEST_DONE]	2	1			T18	1		T182	1		-	-
auto[LP_0]	92	1			T50	4		T183	2		T184	3
auto[LP_021]	29	1			T45	1		T51	2		T52	1
auto[LP_1]	121	1			T50	1		T45	1		T51	1
auto[LP_EVAL]	62	1			T51	1		T13	1		T183	1
auto[LP_SLP]	431	1			T50	7		T45	6		T51	6
auto[LP_PWRUP]	26	1			T45	2		T51	1		T183	1
auto[NP_0]	166	1			T50	1		T45	1		T51	1
auto[NP_021]	28	1			T50	1		T183	1		T178	1
auto[NP_1]	164	1			T50	2		T45	2		T52	4
auto[NP_EVAL]	23	1			T50	1		T178	1		T179	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T13

1

T185

1

T186

1

min

28429

1

T1

6

T2

14

T3

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28433	1			T1	6		T2	14		T3	7
pow[0x1]	13	1			T184	1		T178	1		T180	1
pow[0x2]	16	1			T184	1		T178	1		T179	2
pow[0x3]	24	1			T178	2		T179	3		T53	1
pow[0x4]	75	1			T45	2		T51	2		T52	1
pow[0x5]	120	1			T50	1		T45	2		T52	1
pow[0x6]	228	1			T50	3		T45	3		T51	3
pow[0x7]	464	1			T50	10		T45	6		T51	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

193

1

T50

2

T45

1

T51

2

min

28050

1

T1

6

T2

14

T3

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28050	1			T1	6		T2	14		T3	7
pow[0x6]	1	1			T187	1		-	-		-	-
pow[0x7]	1	1			T188	1		-	-		-	-
pow[0x8]	4	1			T189	2		T190	1		T191	1
pow[0x9]	4	1			T50	1		T192	1		T193	1
pow[0xa]	16	1			T45	1		T184	2		T194	1
pow[0xb]	34	1			T45	1		T15	1		T53	1
pow[0xc]	70	1			T52	3		T15	1		T177	1
pow[0xd]	131	1			T51	2		T52	1		T13	2
pow[0xe]	282	1			T50	2		T45	3		T33	1
pow[0xf]	540	1			T50	10		T45	7		T51	6