Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2148	1			T8	5		T50	12		T32	7
auto[PWRUP]	114	1			T50	2		T33	1		T51	2
auto[ONEST_0]	77	1			T50	1		T45	1		T29	2
auto[ONEST_021]	11	1			T13	1		T15	1		T178	1
auto[ONEST_1]	82	1			T50	2		T33	1		T29	1
auto[ONEST_DONE]	1	1			T334	1		-	-		-	-
auto[LP_0]	124	1			T50	4		T34	3		T51	1
auto[LP_021]	35	1			T50	1		T52	1		T183	2
auto[LP_1]	133	1			T45	2		T33	1		T34	1
auto[LP_EVAL]	52	1			T45	1		T34	1		T29	1
auto[LP_SLP]	466	1			T50	5		T32	2		T45	3
auto[LP_PWRUP]	31	1			T13	1		T183	2		T184	1
auto[NP_0]	186	1			T50	1		T32	1		T45	2
auto[NP_021]	51	1			T33	2		T183	1		T184	1
auto[NP_1]	230	1			T50	1		T32	2		T45	2
auto[NP_EVAL]	30	1			T12	1		T51	3		T183	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T52

1

T178

1

T179

1

min

1839

1

T8

5

T50

5

T32

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1845	1			T8	5		T50	5		T32	11
pow[0x1]	10	1			T334	1		T92	1		T54	1
pow[0x2]	16	1			T14	1		T189	2		T16	1
pow[0x3]	36	1			T50	1		T32	1		T33	1
pow[0x4]	66	1			T50	1		T51	2		T183	1
pow[0x5]	115	1			T50	1		T52	2		T13	4
pow[0x6]	219	1			T50	4		T45	4		T51	6
pow[0x7]	514	1			T50	2		T45	1		T33	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

171

1

T50

4

T45

2

T12

1

min

1350

1

T8

5

T50

1

T32

9

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1357	1			T8	5		T50	1		T32	9
pow[0x1]	9	1			T14	2		T155	1		T168	1
pow[0x2]	26	1			T32	3		T33	4		T14	1
pow[0x3]	42	1			T12	2		T29	1		T13	1
pow[0x4]	38	1			T15	2		T35	1		T155	1
pow[0x5]	1	1			T335	1		-	-		-	-
pow[0x8]	6	1			T53	1		T258	1		T187	1
pow[0x9]	6	1			T336	1		T181	1		T267	1
pow[0xa]	14	1			T50	1		T16	1		T337	1
pow[0xb]	30	1			T29	1		T177	1		T179	1
pow[0xc]	69	1			T51	1		T52	2		T183	1
pow[0xd]	118	1			T50	3		T34	1		T51	2
pow[0xe]	273	1			T50	6		T45	2		T51	2
pow[0xf]	540	1			T50	4		T45	5		T33	1