Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1865	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1992	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1902	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2067	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2146	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2048	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2120	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1961	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1843	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2023	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2020	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2006	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2002	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2013	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2078	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2039	0	0
adc_en_ctl_rd_A	2147483647	1610	0	0
adc_fsm_rst_rd_A	2147483647	1416	0	0
adc_intr_ctl_rd_A	2147483647	1903	0	0
adc_lp_sample_ctl_rd_A	2147483647	1469	0	0
adc_pd_ctl_rd_A	2147483647	1983	0	0
adc_sample_ctl_rd_A	2147483647	1494	0	0
adc_wakeup_ctl_rd_A	2147483647	1624	0	0
intr_enable_rd_A	2147483647	2265	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1865	0	0
T12	603355	3	0	0
T13	0	12	0	0
T14	0	29	0	0
T15	0	39	0	0
T16	0	21	0	0
T17	0	38	0	0
T18	0	26	0	0
T19	0	42	0	0
T20	0	25	0	0
T21	0	16	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T12	603355	15	0	0
T13	0	31	0	0
T14	0	22	0	0
T15	0	40	0	0
T16	0	12	0	0
T17	0	40	0	0
T18	0	45	0	0
T19	0	28	0	0
T20	0	24	0	0
T21	0	37	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1902	0	0
T12	603355	19	0	0
T13	0	22	0	0
T14	0	28	0	0
T15	0	37	0	0
T16	0	18	0	0
T17	0	32	0	0
T18	0	41	0	0
T19	0	24	0	0
T20	0	22	0	0
T21	0	25	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T12	603355	10	0	0
T13	0	17	0	0
T14	0	36	0	0
T15	0	33	0	0
T16	0	20	0	0
T17	0	39	0	0
T18	0	34	0	0
T19	0	33	0	0
T20	0	21	0	0
T21	0	38	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2146	0	0
T12	603355	24	0	0
T13	0	17	0	0
T14	0	29	0	0
T15	0	38	0	0
T16	0	26	0	0
T17	0	41	0	0
T18	0	38	0	0
T19	0	60	0	0
T20	0	34	0	0
T21	0	19	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T12	603355	18	0	0
T13	0	29	0	0
T14	0	13	0	0
T15	0	34	0	0
T16	0	15	0	0
T17	0	53	0	0
T18	0	27	0	0
T19	0	39	0	0
T20	0	19	0	0
T21	0	25	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120	0	0
T12	603355	11	0	0
T13	0	26	0	0
T14	0	19	0	0
T15	0	20	0	0
T16	0	21	0	0
T17	0	28	0	0
T18	0	33	0	0
T19	0	35	0	0
T20	0	43	0	0
T21	0	34	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1961	0	0
T12	603355	24	0	0
T13	0	12	0	0
T14	0	10	0	0
T15	0	40	0	0
T16	0	13	0	0
T17	0	36	0	0
T18	0	24	0	0
T19	0	41	0	0
T20	0	43	0	0
T21	0	22	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1843	0	0
T12	603355	10	0	0
T13	0	16	0	0
T14	0	19	0	0
T15	0	36	0	0
T16	0	18	0	0
T17	0	19	0	0
T18	0	32	0	0
T19	0	54	0	0
T20	0	18	0	0
T21	0	25	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2023	0	0
T12	603355	16	0	0
T13	0	10	0	0
T14	0	19	0	0
T15	0	28	0	0
T16	0	17	0	0
T17	0	35	0	0
T18	0	31	0	0
T19	0	25	0	0
T20	0	19	0	0
T21	0	37	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2020	0	0
T12	603355	23	0	0
T13	0	34	0	0
T14	0	22	0	0
T15	0	35	0	0
T16	0	9	0	0
T17	0	7	0	0
T18	0	28	0	0
T19	0	24	0	0
T20	0	27	0	0
T21	0	28	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2006	0	0
T12	603355	13	0	0
T13	0	20	0	0
T14	0	6	0	0
T15	0	41	0	0
T16	0	23	0	0
T17	0	20	0	0
T18	0	21	0	0
T19	0	33	0	0
T20	0	31	0	0
T21	0	30	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T12	603355	19	0	0
T13	0	37	0	0
T14	0	17	0	0
T15	0	16	0	0
T16	0	18	0	0
T17	0	45	0	0
T18	0	36	0	0
T19	0	59	0	0
T20	0	22	0	0
T21	0	35	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2013	0	0
T12	603355	14	0	0
T13	0	24	0	0
T14	0	11	0	0
T15	0	35	0	0
T16	0	26	0	0
T17	0	41	0	0
T18	0	31	0	0
T19	0	53	0	0
T20	0	20	0	0
T21	0	32	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2078	0	0
T12	603355	11	0	0
T13	0	9	0	0
T14	0	25	0	0
T15	0	38	0	0
T16	0	9	0	0
T17	0	21	0	0
T18	0	27	0	0
T19	0	37	0	0
T20	0	41	0	0
T21	0	27	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2039	0	0
T12	603355	23	0	0
T13	0	14	0	0
T14	0	17	0	0
T15	0	48	0	0
T16	0	26	0	0
T17	0	30	0	0
T18	0	38	0	0
T19	0	18	0	0
T20	0	43	0	0
T21	0	36	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T12	603355	12	0	0
T13	0	22	0	0
T14	0	5	0	0
T15	0	40	0	0
T16	0	20	0	0
T17	0	15	0	0
T18	0	35	0	0
T19	0	50	0	0
T20	0	18	0	0
T21	0	17	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1416	0	0
T12	603355	22	0	0
T13	0	28	0	0
T14	0	16	0	0
T15	0	36	0	0
T16	0	24	0	0
T17	0	35	0	0
T18	0	35	0	0
T19	0	37	0	0
T20	0	32	0	0
T21	0	35	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1903	0	0
T12	603355	6	0	0
T13	0	16	0	0
T14	0	21	0	0
T15	0	29	0	0
T16	0	16	0	0
T17	0	46	0	0
T18	0	32	0	0
T19	0	37	0	0
T20	0	27	0	0
T21	0	33	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469	0	0
T12	603355	14	0	0
T13	0	8	0	0
T14	0	17	0	0
T15	0	35	0	0
T16	0	15	0	0
T17	0	32	0	0
T18	0	32	0	0
T19	0	36	0	0
T20	0	35	0	0
T21	0	24	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1983	0	0
T12	603355	14	0	0
T13	0	6	0	0
T14	0	36	0	0
T15	0	45	0	0
T16	0	26	0	0
T17	0	29	0	0
T18	0	20	0	0
T19	0	47	0	0
T20	0	41	0	0
T21	0	34	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1494	0	0
T12	603355	12	0	0
T13	0	15	0	0
T14	0	17	0	0
T15	0	32	0	0
T16	0	15	0	0
T17	0	30	0	0
T18	0	25	0	0
T19	0	36	0	0
T20	0	36	0	0
T21	0	25	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1624	0	0
T12	603355	6	0	0
T13	0	27	0	0
T14	0	17	0	0
T15	0	21	0	0
T16	0	17	0	0
T17	0	25	0	0
T18	0	33	0	0
T19	0	51	0	0
T20	0	31	0	0
T21	0	19	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2265	0	0
T12	603355	18	0	0
T13	0	43	0	0
T14	0	25	0	0
T15	0	72	0	0
T16	0	50	0	0
T17	0	62	0	0
T18	0	96	0	0
T19	0	57	0	0
T20	0	39	0	0
T22	248347	0	0	0
T23	338855	0	0	0
T24	406450	0	0	0
T25	468794	0	0	0
T26	158024	0	0	0
T27	10482	0	0	0
T28	175470	0	0	0
T29	540643	0	0	0
T30	430185	0	0	0
T31	0	84	0	0