Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6874	1			T3	47		T4	20		T6	68
testmodes[AdcCtrlTestmodeNormal]	5335	1			T1	1		T2	2		T3	45
testmodes[AdcCtrlTestmodeLowpower]	5316	1			T3	50		T5	3		T6	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3812	1			T3	15		T4	19		T6	45
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1678	1			T3	14		T6	16		T12	6
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1271	1			T3	17		T6	7		T12	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1649	1			T3	17		T6	13		T12	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2005	1			T2	1		T3	13		T6	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1337	1			T3	15		T6	9		T7	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1292	1			T3	15		T6	9		T12	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1316	1			T3	17		T6	6		T12	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2468	1			T3	18		T5	2		T6	3