| | | | | | | |
|
prim_sync_reqack |
87.50 |
100.00 |
50.00 |
|
|
100.00 |
100.00 |
|
tlul_rsp_intg_gen |
91.67 |
83.33 |
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen |
100.00 |
|
|
|
|
|
100.00 |
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) |
66.67 |
66.67 |
|
|
|
|
|
|
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) |
100.00 |
100.00 |
|
|
|
|
|
|
adc_ctrl_csr_assert_fpv |
96.00 |
|
|
|
|
|
96.00 |
|
prim_reg_cdc |
97.37 |
100.00 |
89.49 |
|
|
100.00 |
100.00 |
|
prim_reg_cdc |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 ) |
92.31 |
|
92.31 |
|
|
|
|
|
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 ) |
86.67 |
|
86.67 |
|
|
|
|
|
prim_subreg |
97.62 |
100.00 |
92.86 |
|
|
100.00 |
|
|
prim_subreg |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=10,SwAccess=0,RESVAL=0,Mubi=0 + DW=10,SwAccess=1,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=155,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=2,SwAccess=1,RESVAL=0,Mubi=0 ) |
50.00 |
|
50.00 |
|
|
|
|
|
prim_subreg ( parameter DW=24,SwAccess=0,RESVAL=1600,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=7,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
adc_ctrl_fsm |
97.94 |
100.00 |
96.84 |
|
100.00 |
92.86 |
100.00 |
|
prim_reg_cdc_arb |
98.04 |
100.00 |
96.51 |
|
|
95.65 |
100.00 |
|
prim_reg_cdc_arb |
97.83 |
|
|
|
|
95.65 |
100.00 |
|
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=8,ResetVal=4,DstWrReq=0 + DataWidth=16,ResetVal=155,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 ) |
100.00 |
100.00 |
100.00 |
|
|
|
|
|
prim_reg_cdc_arb ( parameter DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 ) |
96.51 |
100.00 |
93.02 |
|
|
|
|
|
tlul_adapter_reg |
98.98 |
100.00 |
95.92 |
|
|
100.00 |
100.00 |
|
adc_ctrl_reg_top |
99.85 |
100.00 |
99.40 |
|
|
100.00 |
100.00 |
|
adc_ctrl |
100.00 |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
tlul_data_integ_dec |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_cmd_intg_chk |
100.00 |
100.00 |
|
|
|
|
100.00 |
|
adc_ctrl_fsm_sva |
100.00 |
|
|
|
|
|
100.00 |
|
prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
|
tlul_assert |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
|
prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
|
adc_ctrl_intr |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_secded_inv_39_32_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_buf |
100.00 |
100.00 |
|
|
|
|
|
|
prim_intr_hw |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_pulse_sync |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_subreg_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
|
prim_subreg_arb |
100.00 |
|
|
|
|
100.00 |
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=24,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 ) |
100.00 |
|
100.00 |
|
|
|
|
|
prim_subreg_arb ( parameter DW=8,SwAccess=3,Mubi=0 + DW=1,SwAccess=3,Mubi=0 ) |
100.00 |
100.00 |
|
|
|
|
|
|
prim_subreg_ext |
100.00 |
100.00 |
|
|
|
|
|
|
adc_ctrl_core |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_secded_inv_39_32_enc |
100.00 |
100.00 |
|
|
|
|
|
|
tlul_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
|
prim_secded_inv_64_57_enc |
100.00 |
100.00 |
|
|
|
|
|
|
prim_secded_inv_64_57_dec |
100.00 |
|
|
100.00 |
|
|
|
|
prim_generic_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
|
tlul_data_integ_enc |
|
|
|
|
|
|
|
|
prim_reg_we_check |
|
|
|
|
|
|
|
|
prim_buf |
|
|
|
|
|
|
|
|
prim_generic_flop_2sync |
|
|
|
|
|
|
|
|
prim_flop |
|
|
|
|
|
|
|
|
prim_flop_2sync |
|
|
|
|
|
|
|
tb |
|
|
|
|
|
|
|