Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19872

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5918

1

T1

1

T2

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20031

1

T1

1

T2

2

T3

142

auto[1]

5759

1

T5

12

T6

1

T7

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38	1			T191	6		T101	3		T158	1
values[1]	736	1			T5	12		T44	19		T118	61
values[2]	649	1			T7	16		T44	2		T25	15
values[3]	835	1			T5	14		T10	1		T12	8
values[4]	640	1			T5	2		T8	17		T12	11
values[5]	633	1			T25	13		T31	12		T141	7
values[6]	633	1			T2	1		T37	5		T143	25
values[7]	565	1			T1	1		T2	1		T143	29
values[8]	586	1			T37	8		T50	1		T39	5
values[9]	3864	1			T6	15		T7	23		T10	2
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	973	1			T5	12		T44	19		T27	1
values[1]	2914	1			T7	16		T11	24		T12	8
values[2]	770	1			T5	14		T10	1		T14	7
values[3]	692	1			T8	17		T12	11		T45	11
values[4]	592	1			T5	2		T25	13		T31	12
values[5]	783	1			T1	1		T2	1		T37	5
values[6]	456	1			T2	1		T217	1		T39	9
values[7]	755	1			T7	23		T10	2		T27	1
values[8]	996	1			T6	14		T144	13		T145	11
values[9]	248	1			T6	1		T14	1		T218	1
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	12		T118	20		T191	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T44	10		T27	1		T118	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	14		T25	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1610	1			T11	24		T12	5		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	14		T10	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	3		T175	1		T219	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	14		T45	11		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	3		T12	7		T146	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	1		T143	12		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	2		T25	1		T141	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T148	1		T155	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T2	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T217	1		T78	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	5		T220	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T37	5		T221	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	12		T10	2		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	7		T145	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T144	1		T198	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T14	1		T222	1		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T6	1		T218	1		T224	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T118	9		T191	5		T148	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	9		T118	16		T142	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	2		T25	14		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1080	1			T12	3		T36	20		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T164	19		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	2		T175	4		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	10		T167	8		T169	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	4		T50	9		T225	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	11		T143	13		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T25	12		T226	12		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T150	2		T228	20		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	2		T143	16		T148	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T230	4		T231	16		T95	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	4		T220	12		T100	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	3		T221	3		T101	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	11		T101	13		T104	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	7		T145	10		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T144	12		T225	2		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T223	10		T169	4		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T224	15		T34	11		T232	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T191	1		T101	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	12		T234	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	12		T118	20		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	10		T118	16		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	14		T25	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T44	1		T27	1		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	14		T10	1		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T12	5		T14	3		T118	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	14		T14	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	2		T8	3		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T31	1		T40	10		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	1		T141	7		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T143	12		T148	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	1		T37	3		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	1		T217	1		T78	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T143	13		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	5		T221	4		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T50	1		T39	3		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T6	7		T14	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1805	1			T6	1		T7	12		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T191	5		T101	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T233	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	9		T148	14		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	9		T118	16		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	2		T25	14		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T142	13		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T164	19		T15	7		T235	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	3		T14	2		T118	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T14	1		T164	10		T167	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	4		T175	4		T225	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T31	11		T40	1		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T25	12		T50	9		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T143	13		T237	6		T238	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	2		T221	1		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T230	4		T229	1		T193	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T143	16		T148	8		T149	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	3		T221	3		T231	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	2		T101	13		T16	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T6	7		T145	10		T220	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1207	1			T7	11		T36	20		T87	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	1		T118	10		T191	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T44	10		T27	1		T118	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	3		T25	15		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1433	1			T11	2		T12	5		T36	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T10	1		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	3		T175	5		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	1		T45	1		T164	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T12	7		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	12		T143	14		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	1		T25	13		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T148	1		T155	1		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	1		T2	1		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T2	1		T217	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	8		T220	13		T100	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	6		T221	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	12		T10	2		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T6	9		T145	11		T220	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T144	13		T198	1		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T14	1		T222	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T6	1		T218	1		T224	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	11		T118	19		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T44	9		T118	15		T142	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	13		T31	2		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1257	1			T11	22		T12	3		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	13		T164	12		T15	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	2		T219	16		T166	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	13		T45	10		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	2		T12	4		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T143	11		T40	3		T83	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T141	6		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T239	10		T228	15		T200	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	12		T15	3		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T78	8		T231	18		T241	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	1		T242	3		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	2		T221	3		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	11		T141	12		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	5		T166	7		T230	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	3		T226	3		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T223	8		T244	6		T169	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T224	10		T245	10		T232	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T191	6		T101	3		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	12		T234	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T118	10		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T44	10		T118	17		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	3		T25	15		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	2		T27	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T10	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	5		T14	3		T118	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	1		T14	2		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T8	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T31	12		T40	8		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	13		T141	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T143	14		T148	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T37	5		T221	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	1		T217	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T143	17		T148	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	6		T221	4		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	1		T39	4		T101	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	470	1			T6	9		T14	1		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1595	1			T6	1		T7	12		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T246	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T233	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	11		T118	19		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	9		T118	15		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	13		T31	2		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	2		T142	12		T39	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	13		T45	10		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	3		T14	2		T118	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	13		T164	10		T83	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T8	2		T12	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	3		T152	12		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T141	6		T146	6		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	11		T241	10		T238	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	3		T240	10		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T78	8		T239	10		T200	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	12		T242	3		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	2		T221	3		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	1		T16	2		T165	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T6	5		T239	10		T152	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1417	1			T7	11		T11	22		T141	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22669

1

T1

1

T2

2

T3

142

auto[ADC_CTRL_FILTER_COND_OUT]

3121

1

T5

12

T6

15

T7

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19797

1

T2

1

T3

142

T4

20

auto[1]

5993

1

T1

1

T2

1

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T249	1		-	-		-	-
values[0]	46	1			T6	1		T151	11		T250	7
values[1]	572	1			T2	1		T7	16		T37	5
values[2]	883	1			T5	2		T14	1		T25	1
values[3]	861	1			T5	12		T10	1		T12	11
values[4]	715	1			T10	1		T12	8		T44	2
values[5]	894	1			T5	14		T6	14		T118	61
values[6]	754	1			T8	14		T14	5		T191	1
values[7]	586	1			T8	3		T14	2		T25	13
values[8]	2799	1			T10	1		T11	24		T36	22
values[9]	1068	1			T1	1		T2	1		T7	23
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	830	1			T2	1		T5	2		T6	1
values[1]	950	1			T5	12		T7	16		T10	1
values[2]	799	1			T10	1		T44	2		T25	1
values[3]	750	1			T5	14		T118	41		T142	47
values[4]	872	1			T6	14		T8	14		T12	8
values[5]	664	1			T8	3		T14	5		T220	13
values[6]	2907	1			T11	24		T36	22		T87	15
values[7]	433	1			T10	1		T25	15		T144	13
values[8]	719	1			T1	1		T2	1		T7	23
values[9]	251	1			T44	19		T143	29		T163	1
minimum	16615	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T5	2		T141	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	1		T37	3		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T50	1		T251	1		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	12		T7	14		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T10	1		T44	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	1		T31	3		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	14		T118	7		T39	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T118	20		T142	24		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T8	14		T12	5		T118	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	7		T221	1		T225	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	3		T220	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	3		T252	1		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T11	24		T36	2		T87	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	1		T163	1		T83	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T144	1		T45	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T25	1		T148	1		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T2	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T27	1		T155	1		T83	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T15	7		T243	11		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T44	10		T143	13		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16469	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T145	10		T175	4		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T37	2		T164	19		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T164	10		T226	9		T165	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	2		T12	4		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	1		T31	11		T191	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T31	2		T37	3		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	5		T39	2		T101	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T118	9		T142	23		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	3		T118	16		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	7		T221	1		T225	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T220	12		T100	9		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	2		T16	15		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T36	20		T87	13		T25	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	1		T15	17		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	12		T221	4		T151	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T25	14		T225	9		T247	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	11		T149	11		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T165	13		T209	8		T253	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T15	7		T18	1		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	9		T143	16		T149	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T151	1		T250	7		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T145	1		T175	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	14		T37	3		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	2		T25	1		T141	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T14	1		T198	1		T146	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T142	1		T50	12		T40	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	12		T10	1		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	1		T12	5		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T37	5		T142	13		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	14		T118	16		T141	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	7		T118	20		T225	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	14		T191	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	3		T221	1		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	3		T25	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	1		T83	3		T15	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T10	1		T11	24		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	1		T163	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T2	1		T7	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T44	10		T27	1		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T151	10		T257	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T145	10		T175	4		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	2		T37	2		T164	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T226	9		T165	4		T228	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	2		T224	15		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	9		T40	1		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	4		T31	2		T142	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	3		T44	1		T31	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	3		T142	13		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T118	16		T148	14		T164	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	7		T118	9		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T220	12		T223	10		T95	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	2		T221	1		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	12		T148	8		T150	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	1		T15	17		T166	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T36	20		T87	13		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T25	14		T167	8		T253	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T7	11		T149	11		T150	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T44	9		T143	16		T149	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1