Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22572

1

T1

1

T2

2

T3

142

auto[ADC_CTRL_FILTER_COND_OUT]

3218

1

T5

12

T6

15

T7

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19809

1

T2

1

T3

142

T4

20

auto[1]

5981

1

T1

1

T2

1

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	176	1			T143	29		T163	1		T155	1
values[0]	10	1			T6	1		T250	7		T267	1
values[1]	635	1			T2	1		T7	16		T37	5
values[2]	877	1			T5	2		T14	1		T198	1
values[3]	849	1			T5	12		T10	1		T12	11
values[4]	730	1			T5	14		T10	1		T44	2
values[5]	865	1			T6	14		T12	8		T118	61
values[6]	756	1			T8	14		T14	5		T191	1
values[7]	588	1			T8	3		T14	2		T25	13
values[8]	2774	1			T10	1		T11	24		T36	22
values[9]	919	1			T1	1		T2	1		T7	23
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	635	1			T5	2		T6	1		T7	16
values[1]	879	1			T5	12		T10	1		T14	1
values[2]	801	1			T12	11		T27	2		T31	17
values[3]	776	1			T5	14		T10	1		T44	2
values[4]	850	1			T6	14		T12	8		T118	32
values[5]	700	1			T8	17		T14	5		T221	2
values[6]	2877	1			T11	24		T36	22		T87	15
values[7]	378	1			T10	1		T25	15		T144	13
values[8]	904	1			T1	1		T2	1		T7	23
values[9]	134	1			T44	19		T15	14		T224	23
minimum	16856	1			T2	1		T3	142		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	2		T141	7		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	1		T7	14		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T25	1		T50	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	12		T10	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T27	1		T31	1		T141	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	7		T27	1		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	14		T10	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T118	20		T142	24		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	5		T118	16		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	7		T225	17		T78	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	17		T220	1		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	3		T221	1		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T11	24		T36	2		T87	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T148	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T10	1		T144	1		T45	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T25	1		T148	1		T225	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T2	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T27	1		T143	13		T149	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T15	7		T243	11		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T44	10		T224	12		T321	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16533	1			T2	1		T3	142		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T219	17		T166	6		T229	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T145	10		T175	4		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	2		T37	2		T164	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T226	9		T165	4		T17	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	2		T164	10		T224	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T31	11		T191	5		T50	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	4		T31	2		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	1		T118	5		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T118	9		T142	23		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	3		T118	16		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	7		T225	14		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T220	12		T100	9		T166	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	2		T221	1		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T36	20		T87	13		T25	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	1		T148	8		T15	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T144	12		T151	18		T101	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T25	14		T225	9		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T7	11		T150	2		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T143	16		T149	14		T165	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T15	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T44	9		T224	11		T322	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T219	9		T166	11		T229	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T163	1		T151	1		T154	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T143	13		T155	1		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T250	7		T267	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T141	7		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	14		T37	3		T164	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T5	2		T50	1		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T14	1		T198	1		T146	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T25	1		T27	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	12		T10	1		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	14		T10	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	5		T142	24		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	5		T118	16		T141	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	7		T118	20		T78	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	14		T191	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	3		T221	1		T225	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	3		T25	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T148	1		T83	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T10	1		T11	24		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T25	1		T163	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T2	1		T7	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T44	10		T27	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T151	9		T154	13		T230	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T143	16		T324	13		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	10		T175	4		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	2		T37	2		T164	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T226	9		T165	4		T283	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	2		T224	15		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	9		T40	1		T226	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	4		T31	2		T221	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	1		T31	11		T118	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	3		T142	23		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	3		T118	16		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	7		T118	9		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T220	12		T223	10		T95	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	2		T221	1		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	12		T150	9		T100	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	1		T148	8		T15	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T36	20		T87	13		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T25	14		T167	8		T265	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	11		T150	2		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T44	9		T149	14		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T141	1		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T7	3		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T25	1		T50	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T10	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T27	1		T31	12		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	7		T27	1		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T10	1		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T118	10		T142	25		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	5		T118	17		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	9		T225	15		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	2		T220	13		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	3		T221	2		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T11	2		T36	22		T87	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	2		T148	9		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	1		T144	13		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	15		T148	1		T225	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T1	1		T2	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T27	1		T143	17		T149	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T15	9		T243	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T44	10		T224	12		T321	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16668	1			T2	1		T3	142		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T219	10		T166	12		T229	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T141	6		T83	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	13		T164	12		T99	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T226	7		T165	4		T17	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	11		T146	6		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T141	12		T50	11		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	4		T31	2		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	13		T118	6		T39	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T118	19		T142	22		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	3		T118	15		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	5		T225	16		T78	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	15		T259	7		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T14	2		T41	3		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T11	22		T260	11		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T83	2		T15	6		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T45	10		T235	1		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T225	8		T265	8		T247	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	11		T221	4		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T143	12		T83	2		T152	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T15	5		T243	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T44	9		T224	11		T321	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T325	19		T246	3		T285	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T219	16		T166	5		T229	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T163	1		T151	10		T154	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T143	17		T155	1		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T250	1		T267	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T141	1		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	3		T37	5		T164	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T50	1		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T198	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T25	1		T27	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T10	1		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T10	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	6		T142	25		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	5		T118	17		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	9		T118	10		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T191	1		T220	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	3		T221	2		T225	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	1		T25	13		T150	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	2		T148	9		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T10	1		T11	2		T36	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T25	15		T163	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T1	1		T2	1		T7	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T44	10		T27	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T243	10		T308	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T143	12		T276	10		T311	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T250	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T141	6		T262	4		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	13		T164	12		T219	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T83	12		T152	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T146	6		T39	1		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T50	11		T40	3		T226	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	11		T12	4		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	13		T118	6		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T37	2		T142	22		T222	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	3		T118	15		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	5		T118	19		T78	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	13		T259	7		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	2		T225	16		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T8	2		T263	10		T236	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T83	2		T15	6		T264	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T11	22		T260	11		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T152	12		T167	17		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	11		T45	10		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	9		T225	8		T83	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24