Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22358

1

T1

1

T2

1

T3

142

auto[ADC_CTRL_FILTER_COND_OUT]

3432

1

T2

1

T5

14

T7

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19696

1

T1

1

T2

1

T3

142

auto[1]

6094

1

T2

1

T5

16

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	228	1			T118	12		T50	1		T273	12
values[0]	10	1			T163	1		T326	9		-	-
values[1]	714	1			T6	1		T27	1		T141	7
values[2]	594	1			T1	1		T7	16		T14	2
values[3]	679	1			T10	2		T12	8		T141	13
values[4]	3075	1			T2	1		T5	12		T11	24
values[5]	760	1			T5	14		T37	8		T39	5
values[6]	853	1			T6	14		T10	1		T25	13
values[7]	697	1			T2	1		T7	23		T8	3
values[8]	635	1			T12	11		T31	12		T142	21
values[9]	934	1			T5	2		T8	14		T14	6
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	632	1			T6	1		T27	1		T191	6
values[1]	752	1			T1	1		T7	16		T10	1
values[2]	640	1			T10	1		T12	8		T27	1
values[3]	3055	1			T2	1		T5	12		T11	24
values[4]	799	1			T5	14		T37	8		T145	11
values[5]	723	1			T6	14		T10	1		T25	13
values[6]	772	1			T2	1		T7	23		T8	3
values[7]	670	1			T12	11		T14	5		T31	12
values[8]	929	1			T5	2		T8	14		T14	1
values[9]	48	1			T327	1		T250	11		T328	1
minimum	16770	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	1		T27	1		T191	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T164	13		T228	16		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T7	14		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T25	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T27	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	5		T142	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	1		T5	12		T11	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T143	12		T149	1		T83	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	5		T39	3		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	14		T145	1		T17	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T6	7		T10	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	20		T148	1		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T25	1		T27	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	1		T7	12		T8	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T31	1		T143	13		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	7		T14	3		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T5	2		T8	14		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	11		T118	7		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T327	1		T171	6		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T250	11		T328	1		T232	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16507	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T150	1		T78	9		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T191	5		T39	2		T101	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T164	19		T228	20		T34	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	2		T14	1		T118	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T280	13		T275	9		T285	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	2		T50	9		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	3		T149	11		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T36	20		T44	1		T87	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T143	13		T149	3		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	3		T39	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T145	10		T17	12		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	7		T25	12		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T118	9		T148	14		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	14		T37	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	11		T44	9		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T31	11		T143	16		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	4		T14	2		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T142	13		T220	12		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T118	5		T220	11		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T171	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T232	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T150	2		T229	8		T169	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T300	13		T285	11		T35	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T118	7		T50	1		T273	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T326	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T27	1		T141	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T150	1		T164	13		T78	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T7	14		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	1		T148	1		T329	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T141	13		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T12	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T2	1		T5	12		T11	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T143	12		T149	2		T83	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	5		T39	3		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	14		T152	18		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	7		T10	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T118	20		T145	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	1		T27	1		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T7	12		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T143	13		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T142	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T5	2		T8	14		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	3		T45	11		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T285	3		T35	10		T171	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T118	5		T273	7		T19	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T191	5		T39	2		T101	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	2		T164	19		T228	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	2		T14	1		T118	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T280	13		T275	9		T281	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	9		T242	7		T165	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	3		T221	3		T226	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T36	20		T44	1		T87	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T143	13		T149	14		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	3		T39	2		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T154	13		T270	11		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	7		T25	12		T148	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T118	9		T145	10		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T25	14		T37	2		T253	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	11		T44	9		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	11		T143	16		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	4		T142	10		T151	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T142	13		T220	12		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	2		T225	14		T220	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T27	1		T191	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	20		T228	21		T34	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	1		T7	3		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	1		T25	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	1		T27	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	5		T142	1		T149	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T2	1		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T143	14		T149	4		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	6		T39	4		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T145	11		T17	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	9		T10	1		T25	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T118	10		T148	15		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T25	15		T27	1		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T7	12		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T31	12		T143	17		T175	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	7		T14	3		T142	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T5	1		T8	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	1		T118	6		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T327	1		T171	4		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T250	1		T328	1		T232	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16634	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T150	3		T78	1		T229	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T235	1		T168	14		T275	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T164	12		T228	15		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	13		T118	15		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T146	6		T241	11		T280	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	2		T141	12		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	3		T221	3		T152	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T5	11		T11	22		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	11		T83	2		T152	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	2		T39	1		T40	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	13		T17	9		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	5		T219	16		T283	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T118	19		T221	4		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T239	10		T224	11		T259	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	11		T8	2		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	12		T16	2		T224	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	4		T14	2		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	1		T8	13		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	10		T118	6		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T171	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T250	10		T232	1		T330	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T141	6		T282	1		T238	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T78	8		T229	11		T331	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T300	1		T285	4		T35	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T118	6		T50	1		T273	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T163	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T326	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	1		T27	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T150	3		T164	20		T78	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	1		T7	3		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T25	1		T148	1		T329	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	1		T141	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T12	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1433	1			T2	1		T5	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T143	14		T149	16		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	6		T39	4		T40	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	1		T152	1		T154	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	9		T10	1		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T118	10		T145	11		T148	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	15		T27	1		T37	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T7	12		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T31	12		T143	17		T175	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	7		T142	11		T151	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T5	1		T8	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	3		T45	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T300	12		T285	10		T35	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T118	6		T19	1		T170	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T326	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T141	6		T235	1		T282	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T164	12		T78	8		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	13		T118	15		T41	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T241	11		T280	18		T275	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T141	12		T50	11		T83	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	3		T146	6		T221	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T5	11		T11	22		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	11		T83	2		T226	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	2		T39	1		T40	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	13		T152	17		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	5		T219	16		T167	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T118	19		T221	4		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T239	10		T262	4		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	11		T8	2		T44	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	12		T16	2		T224	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	4		T142	10		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T8	13		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	2		T45	10		T225	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24