Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22206

1

T1

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3584

1

T2

2

T5

14

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19966

1

T2

1

T3

142

T4

20

auto[1]

5824

1

T1

1

T2

1

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T149	4		T155	1		T259	8
values[0]	65	1			T148	9		T15	7		T18	4
values[1]	701	1			T6	14		T14	2		T31	5
values[2]	793	1			T12	8		T44	19		T14	5
values[3]	596	1			T5	12		T10	2		T225	31
values[4]	690	1			T2	1		T5	14		T7	16
values[5]	2934	1			T7	23		T11	24		T36	22
values[6]	722	1			T8	17		T14	1		T141	3
values[7]	726	1			T2	1		T25	15		T27	1
values[8]	690	1			T25	14		T37	13		T145	11
values[9]	1249	1			T1	1		T5	2		T6	1
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T6	14		T44	19		T14	2
values[1]	847	1			T10	1		T14	5		T142	21
values[2]	635	1			T5	12		T10	1		T12	8
values[3]	2945	1			T2	1		T5	14		T7	16
values[4]	563	1			T7	23		T118	29		T141	7
values[5]	794	1			T8	17		T14	1		T141	3
values[6]	646	1			T2	1		T25	15		T27	1
values[7]	730	1			T5	2		T25	1		T37	8
values[8]	954	1			T1	1		T6	1		T10	1
values[9]	164	1			T118	12		T38	1		T151	10
minimum	16630	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T144	1		T148	1		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T6	7		T44	10		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	1		T14	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T142	11		T218	1		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	12		T12	5		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	1		T31	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T11	24		T12	7		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T5	14		T7	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T118	20		T141	7		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	12		T142	1		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	17		T14	1		T141	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	1		T164	10		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	3		T152	13		T17	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T25	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	2		T37	5		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	1		T143	12		T83	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	1		T6	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	1		T118	16		T141	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T38	1		T151	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T118	7		T166	6		T88	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16475	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T182	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T144	12		T148	8		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	7		T44	9		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	2		T150	9		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T142	10		T101	11		T165	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	3		T50	9		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T31	11		T221	1		T166	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T12	4		T36	20		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	2		T166	7		T253	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T118	9		T39	2		T150	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	11		T143	16		T100	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T148	14		T221	4		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T149	11		T164	10		T15	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	2		T17	12		T231	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T25	14		T101	2		T270	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	3		T145	10		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	13		T101	13		T228	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T25	12		T220	12		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T118	16		T191	5		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T151	9		T289	9		T332	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T118	5		T166	11		T193	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T155	1		T259	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T149	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T148	1		T18	3		T300	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T15	4		T182	9		T284	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T144	1		T39	2		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	7		T14	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	5		T14	3		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T44	10		T142	11		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	12		T10	1		T225	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T166	8		T307	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	7		T44	1		T50	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T5	14		T7	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T11	24		T36	2		T87	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	12		T142	1		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	17		T14	1		T141	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T149	1		T164	10		T15	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T198	1		T225	1		T152	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T25	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	1		T37	8		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T25	1		T143	12		T164	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T1	1		T5	2		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T10	1		T118	23		T141	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T149	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T148	8		T18	1		T269	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T15	3		T284	1		T333	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	12		T39	2		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	7		T14	1		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	3		T14	2		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T44	9		T142	10		T101	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T225	14		T220	11		T104	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T166	7		T307	16		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	4		T44	1		T50	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	2		T31	11		T221	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T36	20		T87	13		T118	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	11		T143	16		T100	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T148	14		T221	4		T258	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	11		T164	10		T15	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	2		T17	12		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	14		T101	2		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T25	12		T37	5		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T143	13		T164	19		T253	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T220	12		T151	9		T15	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T118	21		T191	5		T142	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T144	13		T148	9		T39	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	9		T44	10		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T10	1		T14	3		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T142	11		T218	1		T101	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T12	5		T50	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T31	12		T221	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T11	2		T12	7		T36	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T5	1		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T118	10		T141	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	12		T142	1		T143	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	2		T14	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T149	12		T164	11		T15	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	5		T152	1		T17	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T25	15		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T37	6		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	1		T143	14		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T6	1		T25	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T10	1		T118	17		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T38	1		T151	10		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T118	6		T166	12		T88	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16613	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T182	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	3		T152	34		T262	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	5		T44	9		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	2		T225	16		T239	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T142	10		T165	16		T236	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	11		T12	3		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T83	2		T166	7		T307	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T11	22		T12	4		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	13		T7	13		T239	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T118	19		T141	6		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	11		T143	12		T228	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	15		T141	2		T221	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T164	9		T15	5		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T152	12		T17	9		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	16		T222	13		T325	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T37	2		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T143	11		T83	12		T228	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T226	3		T228	4		T259	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T118	15		T141	12		T142	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T289	2		T332	2		T246	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T118	6		T166	5		T193	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T162	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T182	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T155	1		T259	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T149	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T148	9		T18	3		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T15	4		T182	1		T284	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T144	13		T39	4		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	9		T14	2		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	5		T14	3		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T44	10		T142	11		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T10	1		T225	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T166	8		T307	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	7		T44	2		T50	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T5	1		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T11	2		T36	22		T87	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	12		T142	1		T143	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	2		T14	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T149	12		T164	11		T15	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T198	1		T225	3		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T25	15		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T25	13		T37	11		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T25	1		T143	14		T164	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	1		T5	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T10	1		T118	23		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T259	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T18	1		T300	7		T269	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T15	3		T182	8		T284	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	3		T239	10		T152	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	5		T31	2		T45	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	3		T14	2		T152	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T44	9		T142	10		T275	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	11		T225	16		T242	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T166	7		T307	13		T236	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	4		T50	11		T78	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	13		T7	13		T83	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T11	22		T118	19		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	11		T143	12		T228	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	15		T141	2		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T164	9		T15	5		T167	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T152	12		T17	9		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	16		T222	13		T265	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	2		T225	8		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T143	11		T164	12		T283	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	1		T15	6		T226	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T118	21		T141	12		T142	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24