Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22103

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3687

1

T1

1

T2

1

T5

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19441

1

T3

142

T4

20

T5

26

auto[1]

6349

1

T1

1

T2

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T198	1		T38	1		T218	1
values[0]	56	1			T222	14		T95	13		T334	17
values[1]	659	1			T5	12		T12	19		T25	13
values[2]	705	1			T5	14		T8	14		T10	2
values[3]	628	1			T7	16		T14	3		T37	8
values[4]	564	1			T1	1		T144	13		T141	3
values[5]	587	1			T31	17		T118	32		T150	10
values[6]	637	1			T2	1		T44	19		T25	1
values[7]	681	1			T6	15		T8	3		T10	1
values[8]	648	1			T7	23		T14	5		T118	29
values[9]	3660	1			T2	1		T5	2		T11	24
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	740	1			T5	12		T12	19		T25	13
values[1]	696	1			T5	14		T8	14		T10	2
values[2]	728	1			T7	16		T144	13		T37	8
values[3]	484	1			T1	1		T118	32		T141	3
values[4]	512	1			T31	12		T118	12		T37	5
values[5]	665	1			T2	1		T44	19		T25	1
values[6]	3142	1			T6	15		T7	23		T8	3
values[7]	595	1			T14	5		T118	29		T163	1
values[8]	1301	1			T2	1		T5	2		T27	2
values[9]	159	1			T218	1		T152	18		T258	22
minimum	16768	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	12		T25	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	12		T145	1		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	2		T44	1		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	14		T8	14		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T144	1		T37	5		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	14		T142	1		T239	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T118	16		T217	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T141	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	1		T146	11		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T118	7		T37	3		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	10		T31	3		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T25	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T6	7		T8	3		T11	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	3		T118	20		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	1		T39	2		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T2	1		T5	2		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T27	2		T198	2		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T218	1		T152	18		T258	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T94	1		T229	12		T335	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16531	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T235	3		T34	1		T110	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T25	12		T220	12		T164	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	7		T145	10		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T44	1		T149	11		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T25	14		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T144	12		T37	3		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	2		T228	20		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T118	16		T271	8		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T150	2		T224	11		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T31	11		T150	9		T159	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T118	5		T37	2		T191	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	9		T31	2		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T142	10		T104	4		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T6	7		T36	20		T87	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T142	13		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	2		T118	9		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T149	3		T39	2		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T148	8		T100	9		T16	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T50	9		T39	2		T220	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T258	12		T265	9		T269	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T94	5		T229	8		T335	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T235	1		T95	12		T336	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	1		T218	1		T100	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T198	1		T94	1		T229	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T222	14		T334	17		T268	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T95	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	12		T25	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	12		T40	10		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	2		T44	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	14		T8	14		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	5		T149	1		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	14		T14	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T144	1		T143	13		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T141	3		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T31	4		T118	16		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T224	12		T219	17		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	10		T191	1		T146	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T25	1		T118	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	7		T8	3		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T10	1		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	3		T118	20		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	12		T149	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1761	1			T2	1		T5	2		T11	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T27	2		T198	1		T50	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T100	9		T258	12		T231	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T94	5		T229	8		T337	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T95	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	12		T220	12		T164	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	7		T40	1		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T44	1		T151	10		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T25	14		T145	10		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T37	3		T149	11		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	2		T14	1		T228	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	12		T143	16		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T150	2		T164	10		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	13		T118	16		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T224	11		T219	9		T270	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	9		T221	3		T338	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T118	5		T37	2		T191	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	7		T175	4		T151	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T142	13		T148	14		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	2		T118	9		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	11		T149	3		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T36	20		T87	13		T188	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T50	9		T39	2		T220	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T25	13		T220	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	12		T145	11		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	2		T44	2		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T8	1		T14	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	13		T37	6		T143	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	3		T142	1		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T118	17		T217	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	1		T141	1		T150	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T31	12		T146	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T118	6		T37	5		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	10		T31	3		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T25	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T6	9		T8	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	3		T118	10		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T149	4		T39	4		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T2	1		T5	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T27	2		T198	2		T50	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T218	1		T152	1		T258	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T94	6		T229	9		T335	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16627	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T235	3		T34	1		T110	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	11		T164	22		T283	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	7		T40	3		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	6		T83	12		T15	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	13		T8	13		T141	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T37	2		T143	12		T78	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	13		T239	10		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T118	15		T152	12		T271	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T141	2		T224	11		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T146	10		T159	2		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T118	6		T164	9		T219	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	9		T31	2		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T142	10		T41	3		T165	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T6	5		T8	2		T11	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	11		T142	12		T83	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	2		T118	19		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T239	10		T226	7		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T5	1		T141	6		T39	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	11		T39	1		T226	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T152	17		T258	9		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T229	11		T335	12		T339	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T45	10		T222	13		T334	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T235	1		T257	11		T269	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T38	1		T218	1		T100	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T198	1		T94	6		T229	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T222	1		T334	1		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T95	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T25	13		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	12		T40	8		T225	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	2		T44	2		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T8	1		T25	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T37	6		T149	12		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	3		T14	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T144	13		T143	17		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T141	1		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	15		T118	17		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T224	12		T219	10		T270	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	10		T191	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T25	1		T118	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	9		T8	1		T175	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T10	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	3		T118	10		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	12		T149	4		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T2	1		T5	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T27	2		T198	1		T50	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T258	9		T231	18		T223	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T229	11		T250	6		T337	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T222	13		T334	16		T268	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	11		T45	10		T164	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	7		T40	3		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	6		T83	12		T15	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	13		T8	13		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T37	2		T97	18		T193	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	13		T239	10		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T143	12		T78	8		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	2		T164	9		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T31	2		T118	15		T159	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T224	11		T219	16		T262	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T44	9		T146	10		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T118	6		T142	10		T97	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	5		T8	2		T209	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T142	12		T83	2		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	2		T118	19		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	11		T240	10		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T5	1		T11	22		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T50	11		T39	1		T239	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24