Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22323

1

T2

2

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3467

1

T1

1

T5

16

T6

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19789

1

T1

1

T3

142

T4

20

auto[1]

6001

1

T2

2

T5

26

T6

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	69	1			T142	21		T241	11		T327	1
values[0]	68	1			T118	32		T252	1		T15	14
values[1]	783	1			T5	2		T12	8		T14	2
values[2]	752	1			T5	14		T6	14		T118	12
values[3]	742	1			T25	1		T31	12		T118	29
values[4]	767	1			T2	1		T7	16		T8	14
values[5]	3040	1			T11	24		T36	22		T87	15
values[6]	551	1			T6	1		T14	5		T175	5
values[7]	597	1			T1	1		T7	23		T10	1
values[8]	607	1			T2	1		T5	12		T44	19
values[9]	1203	1			T8	3		T10	1		T25	28
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	972	1			T5	2		T6	14		T12	8
values[1]	804	1			T5	14		T118	12		T37	8
values[2]	633	1			T8	14		T25	1		T31	12
values[3]	3066	1			T2	1		T7	16		T10	1
values[4]	731	1			T6	1		T45	11		T37	5
values[5]	528	1			T12	11		T14	5		T31	5
values[6]	609	1			T1	1		T7	23		T10	1
values[7]	627	1			T2	1		T5	12		T44	19
values[8]	831	1			T8	3		T10	1		T25	15
values[9]	274	1			T27	1		T155	1		T15	7
minimum	16715	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T118	16		T191	1		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	2		T6	7		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T37	5		T141	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	14		T118	7		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	1		T31	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	14		T118	20		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T2	1		T7	14		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T191	1		T220	1		T83	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T37	3		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	11		T146	7		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	3		T251	1		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	7		T31	3		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T27	1		T150	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T5	12		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	10		T14	1		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T141	3		T142	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T8	3		T10	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T155	1		T15	4		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T27	1		T166	8		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16472	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T39	3		T224	11		T304	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T118	16		T191	5		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	7		T12	3		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	3		T221	1		T164	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	5		T101	11		T270	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T31	11		T149	3		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T118	9		T258	12		T236	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1042	1			T7	2		T36	20		T87	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T220	11		T15	17		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	2		T145	10		T225	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T143	13		T50	9		T221	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T14	2		T235	1		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	4		T31	2		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T150	2		T41	3		T97	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	11		T44	1		T101	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T39	2		T306	7		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T44	9		T25	12		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T142	10		T165	4		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T25	14		T144	12		T143	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	3		T341	1		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T166	7		T275	11		T195	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T39	2		T224	15		T304	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T142	11		T241	11		T196	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T327	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T118	16		T342	1		T194	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T252	1		T15	7		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T191	1		T50	1		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	2		T12	5		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	5		T141	7		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	14		T6	7		T118	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T25	1		T31	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T118	20		T198	1		T78	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	1		T7	14		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	14		T220	1		T83	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T11	24		T36	2		T87	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T45	11		T191	1		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T14	3		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T175	1		T225	26		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	1		T150	1		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	1		T5	12		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	10		T14	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T141	3		T148	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T8	3		T10	1		T25	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T142	10		T196	2		T343	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T118	16		T194	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T15	7		T100	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T191	5		T40	1		T221	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	3		T14	1		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	3		T151	28		T307	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	7		T118	5		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T31	11		T149	3		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T118	9		T15	17		T258	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	2		T226	2		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T220	11		T95	12		T335	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T36	20		T87	13		T188	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	13		T50	9		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	2		T225	2		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T175	4		T225	23		T104	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T150	2		T41	3		T306	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	11		T12	4		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T247	15		T170	16		T318	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	9		T148	8		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T39	2		T15	3		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T25	26		T144	12		T143	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T118	17		T191	6		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	1		T6	9		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T37	6		T141	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T118	6		T101	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T25	1		T31	12		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T118	10		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T2	1		T7	3		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T191	1		T220	12		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	1		T37	5		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	1		T146	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T14	3		T251	1		T256	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	7		T31	3		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	1		T150	3		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	1		T5	1		T39	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	10		T14	1		T25	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T141	1		T142	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T8	1		T10	1		T25	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T155	1		T15	4		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T27	1		T166	8		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16618	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	4		T224	16		T304	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T118	15		T40	3		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T6	5		T12	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	2		T141	6		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	13		T118	6		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T83	2		T226	3		T165	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	13		T118	19		T78	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T7	13		T11	22		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T83	12		T15	6		T182	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	9		T222	15		T97	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	10		T146	6		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	2		T235	1		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	4		T31	2		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T41	3		T259	7		T264	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	11		T226	14		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	11		T83	2		T306	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	9		T166	5		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T141	2		T142	10		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	2		T143	12		T39	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	3		T341	7		T325	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T166	7		T275	8		T344	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T345	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T39	1		T224	10		T304	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	11		T241	1		T196	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T327	1		T234	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T118	17		T342	1		T194	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T252	1		T15	9		T100	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T191	6		T50	1		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	1		T12	5		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	6		T141	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T6	9		T118	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T25	1		T31	12		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T118	10		T198	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	1		T7	3		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T220	12		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T11	2		T36	22		T87	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	1		T191	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T14	3		T225	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T175	5		T225	25		T104	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	1		T150	3		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T5	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T44	10		T14	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T141	1		T148	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T8	1		T10	1		T25	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T142	10		T241	10		T196	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T118	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T15	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	3		T219	16		T236	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T12	3		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	2		T141	6		T83	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	13		T6	5		T118	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T164	9		T226	7		T165	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	19		T78	8		T15	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	13		T152	34		T226	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	13		T83	12		T200	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T11	22		T260	11		T177	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	10		T146	6		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	2		T235	1		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T225	24		T16	2		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T41	3		T259	7		T306	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	11		T12	4		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	11		T222	13		T247	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T44	9		T166	5		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T141	2		T83	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T8	2		T143	12		T39	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24