Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22152

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3638

1

T1

1

T2

1

T5

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19786

1

T1

1

T3

142

T4

20

auto[1]

6004

1

T2

2

T5

14

T6

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	324	1			T8	3		T142	21		T148	1
values[0]	37	1			T118	32		T39	5		-	-
values[1]	792	1			T5	2		T12	8		T14	2
values[2]	727	1			T5	14		T6	14		T37	8
values[3]	842	1			T8	14		T25	1		T31	12
values[4]	713	1			T2	1		T7	16		T10	1
values[5]	3011	1			T11	24		T36	22		T87	15
values[6]	569	1			T6	1		T12	11		T14	5
values[7]	661	1			T1	1		T7	23		T10	1
values[8]	519	1			T2	1		T5	12		T44	19
values[9]	984	1			T10	1		T25	28		T27	1
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	836	1			T5	16		T12	8		T118	32
values[1]	776	1			T6	14		T118	41		T37	8
values[2]	662	1			T8	14		T10	1		T25	1
values[3]	3066	1			T2	1		T7	16		T11	24
values[4]	745	1			T6	1		T45	11		T37	5
values[5]	484	1			T12	11		T14	5		T31	5
values[6]	630	1			T1	1		T7	23		T10	1
values[7]	635	1			T2	1		T5	12		T44	19
values[8]	863	1			T8	3		T10	1		T25	15
values[9]	249	1			T27	1		T155	1		T15	7
minimum	16844	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T118	16		T50	1		T40	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	16		T12	5		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	5		T141	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	7		T118	27		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	1		T25	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	14		T198	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T2	1		T7	14		T11	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T191	1		T220	1		T83	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T37	3		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T45	11		T146	7		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T251	1		T256	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	7		T14	3		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	1		T150	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	12		T39	2		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	1		T44	10		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T141	3		T142	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T8	3		T10	1		T25	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T155	1		T15	4		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T27	1		T293	1		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16508	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T14	1		T191	1		T39	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T118	16		T40	1		T219	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	3		T164	10		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T37	3		T221	1		T151	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	7		T118	14		T270	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	11		T149	3		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T150	9		T236	5		T312	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T7	2		T36	20		T87	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T220	11		T15	17		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T37	2		T145	10		T50	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T143	13		T221	4		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T16	15		T235	1		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	4		T14	2		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T150	2		T41	3		T97	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	11		T44	1		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T39	2		T166	18		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T44	9		T25	12		T148	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T142	10		T165	4		T228	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	14		T144	12		T143	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T15	3		T196	2		T346	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T275	11		T347	13		T289	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T14	1		T191	5		T39	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T142	11		T148	1		T155	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T8	3		T293	1		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T118	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T39	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	1		T40	10		T219	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	2		T12	5		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	5		T141	7		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	14		T6	7		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T25	1		T31	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	14		T118	27		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	1		T7	14		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T191	1		T220	1		T83	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T11	24		T36	2		T87	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	11		T146	7		T143	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T225	1		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	7		T14	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T27	1		T150	1		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	12		T192	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T44	10		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T141	3		T39	2		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	1		T25	2		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T142	10		T165	4		T228	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T193	10		T275	9		T20	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T118	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T39	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	1		T219	9		T301	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	3		T14	1		T191	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	3		T221	1		T151	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	7		T164	10		T166	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T31	11		T149	3		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T118	14		T150	9		T231	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	2		T226	2		T154	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T220	11		T15	17		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T36	20		T87	13		T188	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T143	13		T221	4		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T225	2		T16	15		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	4		T14	2		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T150	2		T41	3		T95	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	11		T44	1		T31	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T166	11		T170	16		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T44	9		T148	8		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	2		T15	3		T166	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T25	26		T144	12		T143	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T118	17		T50	1		T40	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	2		T12	5		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T37	6		T141	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	9		T118	16		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T25	1		T31	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T198	1		T150	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	1		T7	3		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T191	1		T220	12		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T6	1		T37	5		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	1		T146	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T251	1		T256	1		T16	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	7		T14	3		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	1		T150	3		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T7	12		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T39	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T44	10		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T141	1		T142	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T8	1		T10	1		T25	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T155	1		T15	4		T340	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T27	1		T293	1		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16658	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T14	2		T191	6		T39	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T118	15		T40	3		T239	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	14		T12	3		T141	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	2		T141	6		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	5		T118	25		T167	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T164	9		T83	2		T226	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	13		T78	8		T236	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T7	13		T11	22		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T83	12		T15	6		T167	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	11		T17	9		T222	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	10		T146	6		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T16	2		T235	1		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	4		T14	2		T31	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T41	3		T259	7		T264	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	11		T142	12		T226	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	11		T83	2		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T44	9		T228	13		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T141	2		T142	10		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	2		T143	12		T39	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T15	3		T196	11		T348	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T275	8		T347	4		T289	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T291	13		T184	12		T197	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T39	1		T209	8		T304	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T142	11		T148	1		T155	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	1		T293	1		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T118	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T39	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	1		T40	8		T219	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	1		T12	5		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	6		T141	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T6	9		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T25	1		T31	12		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T118	16		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T2	1		T7	3		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T191	1		T220	12		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T11	2		T36	22		T87	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	1		T146	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	1		T225	3		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	7		T14	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	1		T150	3		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T192	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	1		T44	10		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T141	1		T39	4		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T10	1		T25	28		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T142	10		T165	4		T228	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	2		T193	7		T275	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T118	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T39	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	3		T219	16		T236	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T12	3		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	2		T141	6		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	13		T6	5		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T164	9		T83	2		T226	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	13		T118	25		T78	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	13		T152	17		T226	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T83	12		T15	6		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T11	22		T260	11		T50	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	10		T146	6		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	2		T235	1		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	4		T14	2		T225	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	3		T259	7		T264	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	11		T31	2		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T5	11		T166	5		T170	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T44	9		T228	13		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T141	2		T83	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T143	12		T39	12		T221	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24