Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	1		T5	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	1		T37	5		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T50	1		T251	1		T164	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	1		T7	3		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T44	2		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T27	1		T31	3		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T118	6		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T118	10		T142	25		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T8	1		T12	5		T118	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	9		T221	2		T225	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T220	13		T100	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	3		T252	1		T16	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T11	2		T36	22		T87	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	2		T163	1		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	1		T144	13		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T25	15		T148	1		T225	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T1	1		T2	1		T7	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	1		T155	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T15	9		T243	1		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T44	10		T143	17		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16612	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T141	6		T83	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T164	12		T219	16		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T164	9		T226	7		T165	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	11		T7	13		T12	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T141	12		T50	11		T40	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	2		T37	2		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	13		T118	6		T39	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T118	19		T142	22		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	13		T12	3		T118	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	5		T225	16		T78	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	2		T259	7		T247	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	2		T16	2		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1223	1			T11	22		T260	11		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T83	2		T15	6		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T45	10		T221	4		T235	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T225	8		T247	15		T261	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	11		T166	7		T228	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T83	2		T152	17		T165	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T15	5		T243	10		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T44	9		T143	12		T224	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T246	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	11		T250	1		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T6	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T145	11		T175	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	3		T37	5		T164	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	1		T25	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T198	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T142	1		T50	10		T40	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T10	1		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	1		T12	5		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T37	6		T142	14		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	1		T118	17		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	9		T118	10		T225	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	1		T191	1		T220	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	3		T221	2		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T25	13		T148	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	2		T83	1		T15	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T10	1		T11	2		T36	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T25	15		T163	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T1	1		T2	1		T7	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T44	10		T27	1		T143	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T250	6		T257	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T262	4		T231	12		T99	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	13		T164	12		T219	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T141	6		T83	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T146	6		T39	1		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T50	11		T40	3		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	11		T12	4		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	3		T118	6		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T37	2		T142	12		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	13		T118	15		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	5		T118	19		T225	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	13		T223	8		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	2		T41	3		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	2		T259	7		T263	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T83	2		T15	6		T264	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T11	22		T260	11		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T152	29		T167	17		T265	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	11		T45	10		T221	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T44	9		T143	12		T225	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24