Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22148

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3642

1

T1

1

T2

1

T5

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19544

1

T3

142

T4

20

T5

26

auto[1]

6246

1

T1

1

T2

2

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T266	5		T267	1		-	-
values[0]	27	1			T222	14		T114	1		T268	12
values[1]	710	1			T5	12		T12	19		T25	13
values[2]	662	1			T5	14		T8	14		T10	2
values[3]	614	1			T7	16		T14	3		T37	8
values[4]	659	1			T1	1		T144	13		T141	3
values[5]	506	1			T31	17		T118	32		T150	10
values[6]	715	1			T2	1		T44	19		T25	1
values[7]	614	1			T6	15		T8	3		T10	1
values[8]	668	1			T7	23		T14	5		T118	29
values[9]	3998	1			T2	1		T5	2		T11	24
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	890	1			T5	12		T12	19		T25	13
values[1]	678	1			T5	14		T8	14		T10	1
values[2]	684	1			T7	16		T10	1		T144	13
values[3]	522	1			T1	1		T118	32		T141	3
values[4]	563	1			T31	17		T118	12		T37	5
values[5]	627	1			T2	1		T6	14		T44	19
values[6]	3074	1			T6	1		T10	1		T11	24
values[7]	670	1			T7	23		T8	3		T14	5
values[8]	1202	1			T2	1		T5	2		T27	2
values[9]	248	1			T148	9		T218	1		T152	18
minimum	16632	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	12		T25	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	12		T145	1		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	1		T44	1		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	14		T8	14		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	1		T144	1		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	14		T142	1		T78	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T118	16		T217	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T141	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T31	4		T146	11		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T118	7		T37	3		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	7		T44	10		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	1		T25	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T10	1		T11	24		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	1		T142	13		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	3		T14	3		T118	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	12		T149	1		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T2	1		T5	2		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T27	2		T198	2		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T148	1		T218	1		T152	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T230	1		T229	12		T161	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16477	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T269	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	12		T220	12		T164	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	7		T145	10		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T44	1		T149	11		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T25	14		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	12		T37	3		T143	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	2		T228	20		T270	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T118	16		T271	8		T236	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T150	2		T224	11		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T31	13		T150	9		T272	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T118	5		T37	2		T191	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	7		T44	9		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T142	10		T104	4		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T36	20		T87	13		T188	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	13		T148	14		T101	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	2		T118	9		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	11		T149	3		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T100	9		T226	2		T16	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T50	9		T39	2		T220	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T148	8		T258	12		T230	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T229	8		T161	10		T193	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T266	4		T267	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	14		T114	1		T268	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	12		T25	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	12		T40	10		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	2		T44	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	14		T8	14		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	5		T149	1		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	14		T14	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	1		T143	13		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T141	3		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	4		T118	16		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T224	12		T219	17		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T44	10		T146	11		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T25	1		T118	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	7		T8	3		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T142	13		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	3		T118	20		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	12		T149	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1878	1			T2	1		T5	2		T11	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	449	1			T27	2		T198	2		T50	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	12		T220	12		T164	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	7		T40	1		T225	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T44	1		T151	10		T101	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	14		T145	10		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T37	3		T149	11		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	2		T14	1		T228	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T144	12		T143	16		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T150	2		T164	10		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	13		T118	16		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T224	11		T219	9		T270	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	9		T221	3		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T118	5		T37	2		T191	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	7		T175	4		T151	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T142	13		T148	14		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	2		T118	9		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	11		T149	3		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T36	20		T87	13		T188	29
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T50	9		T39	2		T220	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T25	13		T220	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	12		T145	11		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	1		T44	2		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T8	1		T14	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	1		T144	13		T37	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	3		T142	1		T78	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T118	17		T217	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T141	1		T150	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	15		T146	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T118	6		T37	5		T191	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	9		T44	10		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	1		T25	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T10	1		T11	2		T36	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	1		T142	14		T148	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	1		T14	3		T118	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	12		T149	4		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T2	1		T5	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T27	2		T198	2		T50	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T148	9		T218	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T230	1		T229	9		T161	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16613	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T269	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	11		T164	22		T222	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	7		T40	3		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	6		T83	12		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	13		T8	13		T141	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	2		T143	12		T152	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	13		T78	8		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T118	15		T241	4		T271	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T141	2		T224	11		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T31	2		T146	10		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	6		T164	9		T219	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	5		T44	9		T221	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	10		T41	3		T165	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T11	22		T260	11		T177	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	12		T83	2		T152	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	2		T14	2		T118	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	11		T226	7		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	1		T141	6		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T50	11		T39	13		T239	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T152	17		T258	9		T230	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T229	11		T161	2		T193	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T45	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T269	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T266	2		T267	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T222	1		T114	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T25	13		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	12		T40	8		T225	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	2		T44	2		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T8	1		T25	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T37	6		T149	12		T252	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	3		T14	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	13		T143	17		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T141	1		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	15		T118	17		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T224	12		T219	10		T270	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	10		T146	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T25	1		T118	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	9		T8	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T142	14		T148	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	3		T118	10		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	12		T149	4		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1681	1			T2	1		T5	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	464	1			T27	2		T198	2		T50	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T266	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T222	13		T268	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	11		T45	10		T164	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T40	3		T15	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T146	6		T83	12		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	13		T8	13		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	2		T97	18		T193	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	13		T239	10		T228	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	12		T152	12		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T141	2		T164	9		T78	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T31	2		T118	15		T248	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T224	11		T219	16		T159	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	9		T146	10		T221	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T118	6		T142	10		T97	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T6	5		T8	2		T238	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T142	12		T83	2		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	2		T118	19		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	11		T240	10		T167	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T5	1		T11	22		T141	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T50	11		T39	13		T239	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24