Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22359

1

T1

1

T2

1

T3

142

auto[ADC_CTRL_FILTER_COND_OUT]

3431

1

T2

1

T5

14

T7

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19696

1

T1

1

T2

1

T3

142

auto[1]

6094

1

T2

1

T5

16

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T273	12		-	-		-	-
values[0]	58	1			T163	1		T196	12		T266	37
values[1]	685	1			T6	1		T7	16		T27	1
values[2]	593	1			T1	1		T14	2		T25	1
values[3]	670	1			T10	2		T12	8		T141	13
values[4]	3035	1			T2	1		T5	12		T11	24
values[5]	767	1			T5	14		T40	11		T150	10
values[6]	856	1			T6	14		T7	23		T10	1
values[7]	662	1			T2	1		T8	3		T44	19
values[8]	738	1			T12	11		T27	1		T31	12
values[9]	1103	1			T5	2		T8	14		T14	6
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T6	1		T27	1		T141	7
values[1]	761	1			T1	1		T7	16		T10	1
values[2]	631	1			T10	1		T12	8		T27	1
values[3]	3034	1			T2	1		T5	12		T11	24
values[4]	834	1			T5	14		T37	8		T145	11
values[5]	691	1			T6	14		T10	1		T25	13
values[6]	783	1			T2	1		T7	23		T8	3
values[7]	639	1			T31	12		T142	21		T143	29
values[8]	878	1			T8	14		T14	5		T118	12
values[9]	148	1			T5	2		T14	1		T45	11
minimum	16643	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T6	1		T27	1		T141	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T150	1		T164	13		T78	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T7	14		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	1		T25	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	1		T27	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	5		T142	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T2	1		T5	12		T11	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T143	12		T149	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	5		T39	3		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	14		T145	1		T17	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	7		T10	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T118	20		T148	1		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T25	1		T27	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T7	12		T8	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T31	1		T143	13		T175	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T142	11		T225	17		T164	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T8	14		T141	3		T142	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	3		T118	7		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	2		T14	1		T231	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T45	11		T158	1		T250	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16474	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T274	1		T197	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T39	2		T101	2		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T150	2		T164	19		T228	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	2		T14	1		T118	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T193	10		T275	9		T195	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	2		T50	9		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	3		T149	11		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T36	20		T44	1		T87	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	13		T149	3		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	3		T39	2		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T145	10		T17	12		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	7		T25	12		T148	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T118	9		T148	14		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	14		T37	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	11		T12	4		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	11		T143	16		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T142	10		T225	14		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T142	13		T220	12		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	2		T118	5		T220	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T231	16		T171	3		T276	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T232	14		T277	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T273	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T163	1		T196	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T266	19		T278	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T7	14		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T150	1		T164	13		T78	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T14	1		T118	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	1		T148	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	1		T141	13		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	1		T12	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T2	1		T5	12		T11	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T143	12		T149	2		T83	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	10		T150	1		T279	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	14		T152	18		T17	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	7		T10	1		T25	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	12		T118	20		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T25	1		T37	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T8	3		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	1		T31	1		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	7		T142	11		T225	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T5	2		T8	14		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T14	3		T45	11		T118	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T273	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T196	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T266	18		T278	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	2		T191	5		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	2		T164	19		T228	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	1		T118	16		T221	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T280	13		T275	9		T281	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T50	9		T242	7		T95	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	3		T221	3		T226	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T36	20		T44	1		T87	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T143	13		T149	14		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	1		T150	9		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	12		T154	13		T270	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	7		T25	12		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	11		T118	9		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	14		T37	2		T253	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T44	9		T144	12		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T31	11		T143	16		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	4		T142	10		T225	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T142	13		T220	12		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	2		T118	5		T220	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	1		T27	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T150	3		T164	20		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T1	1		T7	3		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	1		T25	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	1		T27	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	5		T142	1		T149	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T2	1		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T143	14		T149	4		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T37	6		T39	4		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T145	11		T17	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	9		T10	1		T25	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T118	10		T148	15		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	15		T27	1		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T7	12		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T31	12		T143	17		T175	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T142	11		T225	15		T164	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T8	1		T141	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	3		T118	6		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T5	1		T14	1		T231	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T45	1		T158	1		T250	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16622	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T274	1		T197	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T141	6		T235	1		T282	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T164	12		T78	8		T228	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	13		T118	15		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	6		T222	15		T241	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T31	2		T141	12		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	3		T221	3		T152	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T5	11		T11	22		T260	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T143	11		T83	2		T152	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	2		T39	1		T40	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	13		T17	9		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	5		T283	14		T113	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T118	19		T221	4		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T239	10		T224	11		T259	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	11		T8	2		T12	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T143	12		T224	10		T166	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T142	10		T225	16		T164	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	13		T141	2		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	2		T118	6		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T5	1		T231	18		T171	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T45	10		T250	10		T232	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T196	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T197	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T273	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T163	1		T196	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T266	19		T278	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	1		T7	3		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T150	3		T164	20		T78	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	1		T14	2		T118	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T25	1		T148	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	1		T141	1		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T12	5		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T2	1		T5	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T143	14		T149	16		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	8		T150	10		T279	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	1		T152	1		T17	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	9		T10	1		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	12		T118	10		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	15		T37	5		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T8	1		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	1		T31	12		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	7		T142	11		T225	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T5	1		T8	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	3		T45	1		T118	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T196	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T266	18		T278	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	13		T141	6		T235	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T164	12		T78	8		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T118	15		T41	3		T165	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T241	11		T280	18		T275	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	12		T50	11		T83	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	3		T146	6		T221	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T5	11		T11	22		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	11		T83	2		T226	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	3		T15	3		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	13		T152	17		T17	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	5		T37	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	11		T118	19		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T239	10		T262	4		T243	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	2		T44	9		T225	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	12		T16	2		T224	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	4		T142	10		T225	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T5	1		T8	13		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	2		T45	10		T118	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24