Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22135

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3655

1

T1

1

T2

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19622

1

T2

2

T3

142

T4

20

auto[1]

6168

1

T1

1

T5

26

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	269	1			T14	2		T164	21		T239	11
values[0]	17	1			T284	3		T285	14		-	-
values[1]	759	1			T7	23		T44	19		T145	11
values[2]	3031	1			T2	1		T11	24		T12	11
values[3]	532	1			T5	2		T7	16		T12	8
values[4]	696	1			T1	1		T10	1		T44	2
values[5]	777	1			T8	3		T10	1		T27	1
values[6]	746	1			T5	12		T8	14		T14	1
values[7]	762	1			T25	1		T144	13		T142	21
values[8]	733	1			T5	14		T10	1		T118	29
values[9]	857	1			T2	1		T6	15		T27	2
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	828	1			T2	1		T7	23		T14	5
values[1]	2931	1			T11	24		T12	19		T36	22
values[2]	482	1			T5	2		T7	16		T10	1
values[3]	688	1			T1	1		T10	1		T44	2
values[4]	821	1			T8	3		T14	1		T25	13
values[5]	788	1			T5	12		T8	14		T25	15
values[6]	754	1			T25	1		T118	29		T142	21
values[7]	742	1			T5	14		T10	1		T31	5
values[8]	791	1			T2	1		T6	14		T14	2
values[9]	130	1			T6	1		T149	4		T164	21
minimum	16835	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T191	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	12		T14	3		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T11	24		T36	2		T87	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	12		T141	13		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	2		T155	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	14		T10	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T44	1		T141	3		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T10	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	3		T27	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T25	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	12		T25	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	14		T118	16		T146	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T78	9		T15	8		T226	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T25	1		T118	20		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	14		T10	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	13		T164	10		T83	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	7		T14	1		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	1		T118	7		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T149	1		T286	1		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T6	1		T164	11		T239	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16510	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T44	10		T217	1		T16	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T191	5		T145	10		T150	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	11		T14	2		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T36	20		T87	13		T188	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T12	7		T265	9		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T271	12		T227	11		T193	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	2		T50	9		T150	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T44	1		T15	3		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T37	2		T143	13		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T31	11		T37	3		T225	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T25	12		T148	14		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	14		T144	12		T143	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T118	16		T101	2		T228	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	17		T226	12		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T118	9		T142	10		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T31	2		T220	12		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T142	13		T164	10		T101	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	7		T14	1		T164	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T118	5		T39	2		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T149	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T164	10		T193	10		T287	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T44	9		T16	15		T219	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T14	1		T226	8		T166	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T164	11		T239	11		T113	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T284	2		T285	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T145	1		T50	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	12		T44	10		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T2	1		T11	24		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	7		T14	3		T141	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	2		T45	11		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	14		T12	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T44	1		T141	3		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T10	1		T37	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	3		T27	1		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T148	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	12		T25	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	14		T14	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T144	1		T175	1		T78	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T25	1		T142	11		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	14		T10	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T118	20		T142	13		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	7		T27	2		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	1		T6	1		T118	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T14	1		T226	9		T166	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T164	10		T113	14		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T284	1		T285	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	10		T150	9		T221	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	11		T44	9		T151	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T36	20		T87	13		T188	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	4		T14	2		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	9		T228	15		T271	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T7	2		T12	3		T50	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T44	1		T15	3		T230	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	2		T143	13		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	3		T225	14		T151	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	14		T39	2		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	14		T31	11		T143	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	12		T118	16		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T144	12		T175	4		T15	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T142	10		T220	11		T235	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T220	12		T226	12		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T118	9		T142	13		T148	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	7		T31	2		T149	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T118	5		T39	2		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	1		T191	6		T145	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	12		T14	3		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T11	2		T36	22		T87	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	12		T141	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T155	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	3		T10	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	2		T141	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	1		T10	1		T37	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T27	1		T31	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	1		T25	13		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T25	15		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T118	17		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T78	1		T15	19		T226	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	1		T118	10		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T10	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T142	14		T164	11		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	9		T14	2		T27	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T118	6		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T149	4		T286	1		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T6	1		T164	11		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16660	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T44	10		T217	1		T16	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T221	3		T166	7		T228	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	11		T14	2		T243	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T11	22		T45	10		T260	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	7		T141	12		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	1		T152	17		T227	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T7	13		T50	11		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T141	2		T15	3		T152	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T143	11		T40	3		T242	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	2		T37	2		T141	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T221	4		T224	10		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	11		T143	12		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	13		T118	15		T146	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T78	8		T15	6		T226	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T118	19		T142	10		T235	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	13		T31	2		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	12		T164	9		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	5		T164	12		T226	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T118	6		T39	1		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T164	10		T239	10		T99	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T17	9		T288	6		T284	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T44	9		T16	2		T219	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T14	2		T226	10		T166	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T164	11		T239	1		T113	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T284	2		T285	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T145	11		T50	1		T150	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	12		T44	10		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	1		T11	2		T36	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	7		T14	3		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T45	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	3		T12	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	2		T141	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T10	1		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	1		T27	1		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	1		T148	15		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T25	15		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T14	1		T25	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T144	13		T175	5		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	1		T142	11		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T10	1		T220	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T118	10		T142	14		T148	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	9		T27	2		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T6	1		T118	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T226	7		T166	7		T289	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T164	10		T239	10		T113	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	1		T285	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T166	7		T17	9		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	11		T44	9		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T11	22		T260	11		T177	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	4		T14	2		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T45	10		T152	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T7	13		T12	3		T50	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T141	2		T15	3		T152	34
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T143	11		T167	17		T159	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	2		T37	2		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	3		T224	10		T242	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	11		T146	6		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	13		T118	15		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T78	8		T15	6		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T142	10		T235	1		T258	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	13		T226	14		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T118	19		T142	12		T83	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	5		T31	2		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T118	6		T39	1		T225	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24