Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19825

1

T2

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5965

1

T1

1

T2

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20005

1

T2

2

T3

142

T4

20

auto[1]

5785

1

T1

1

T5

12

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	310	1			T279	1		T224	26		T290	4
values[0]	2	1			T158	1		T234	1		-	-
values[1]	746	1			T5	12		T44	19		T118	61
values[2]	709	1			T7	16		T44	2		T25	15
values[3]	779	1			T5	14		T10	1		T12	8
values[4]	669	1			T5	2		T8	17		T12	11
values[5]	564	1			T25	13		T31	12		T141	7
values[6]	694	1			T2	1		T37	5		T143	25
values[7]	615	1			T1	1		T2	1		T143	29
values[8]	500	1			T37	8		T50	1		T221	7
values[9]	3591	1			T6	15		T7	23		T10	2
minimum	16611	1			T3	142		T4	20		T6	115

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	749	1			T27	1		T118	61		T142	22
values[1]	2998	1			T7	16		T11	24		T12	8
values[2]	776	1			T5	14		T10	1		T14	7
values[3]	602	1			T5	2		T8	17		T12	11
values[4]	614	1			T25	13		T31	12		T141	7
values[5]	739	1			T1	1		T2	1		T37	5
values[6]	495	1			T2	1		T217	1		T39	9
values[7]	712	1			T7	23		T10	2		T37	8
values[8]	1132	1			T6	15		T27	1		T144	13
values[9]	142	1			T14	1		T224	26		T34	12
minimum	16831	1			T3	142		T4	20		T5	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T118	20		T142	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T27	1		T118	16		T142	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	14		T25	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1613	1			T11	24		T12	5		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	14		T10	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T14	3		T226	8		T219	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	14		T164	11		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	2		T8	3		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T31	1		T143	12		T40	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	1		T141	7		T146	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T148	1		T155	2		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T2	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	1		T217	1		T78	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	5		T221	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	5		T221	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	12		T10	2		T141	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T6	7		T145	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	1		T27	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T14	1		T222	1		T223	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T224	11		T34	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16535	1			T3	142		T4	20		T5	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T44	10		T241	12		T250	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T118	9		T148	14		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T118	16		T142	10		T15	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T25	14		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1092	1			T12	3		T36	20		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	1		T164	19		T15	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	2		T226	9		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T164	10		T167	8		T169	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	4		T50	9		T175	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T31	11		T143	13		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T25	12		T225	14		T226	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T150	2		T228	20		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	2		T143	16		T148	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T230	4		T231	16		T193	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	4		T221	1		T220	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	3		T221	3		T101	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	11		T101	13		T104	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	7		T145	10		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	12		T225	2		T151	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T223	10		T169	4		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T224	15		T34	11		T290	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T44	1		T45	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T44	9		T291	22		T278	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T279	1		T292	1		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T224	11		T290	1		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T158	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	12		T118	20		T191	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	10		T118	16		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	14		T25	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T44	1		T27	1		T118	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	14		T10	1		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	5		T14	3		T226	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	14		T14	1		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	2		T8	3		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T31	1		T40	10		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	1		T141	7		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T143	12		T155	1		T228	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T37	3		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	1		T217	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T143	13		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	5		T221	4		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T50	1		T101	1		T16	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T6	7		T14	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1764	1			T6	1		T7	12		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16465	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T223	10		T169	4		T294	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T224	15		T290	3		T280	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T118	9		T191	5		T148	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	9		T118	16		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	2		T25	14		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	1		T118	5		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	19		T15	7		T235	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	3		T14	2		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	1		T164	10		T167	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	4		T175	4		T225	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T31	11		T40	1		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T25	12		T50	9		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	13		T228	20		T237	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	2		T149	3		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T230	4		T231	16		T229	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T143	16		T148	8		T39	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T37	3		T221	3		T258	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T101	13		T16	15		T165	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	7		T145	10		T220	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1186	1			T7	11		T36	20		T87	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T118	10		T142	1		T148	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T27	1		T118	17		T142	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T25	15		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1448	1			T11	2		T12	5		T36	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T10	1		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	3		T226	10		T219	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T164	11		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T8	1		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	12		T143	14		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	13		T141	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T148	1		T155	2		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	1		T2	1		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	1		T217	1		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	8		T221	2		T220	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	6		T221	4		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	12		T10	2		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T6	9		T145	11		T220	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T6	1		T27	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T14	1		T222	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T224	16		T34	12		T290	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16651	1			T3	142		T4	20		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T44	10		T241	1		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T118	19		T221	4		T17	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T118	15		T142	10		T83	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	13		T31	2		T209	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1257	1			T11	22		T12	3		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	13		T45	10		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	2		T226	7		T219	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	13		T164	10		T167	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T8	2		T12	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T143	11		T40	3		T83	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T141	6		T146	6		T225	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T239	10		T228	15		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	12		T15	3		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T78	8		T231	18		T193	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	1		T242	3		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	2		T221	3		T239	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	11		T141	12		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T6	5		T166	7		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T41	3		T226	3		T222	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T223	8		T244	6		T169	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T224	10		T295	13		T296	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T5	11		T247	10		T297	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T44	9		T241	11		T250	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T279	1		T292	1		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T224	16		T290	4		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T158	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T234	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T118	10		T191	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T44	10		T118	17		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	3		T25	15		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	2		T27	1		T118	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T10	1		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	5		T14	3		T226	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	1		T14	2		T25	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T8	1		T12	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	12		T40	8		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	13		T141	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T143	14		T155	1		T228	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T37	5		T149	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T217	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T143	17		T148	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	6		T221	4		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	1		T101	14		T16	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T6	9		T14	1		T145	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1569	1			T6	1		T7	12		T10	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	142		T4	20		T6	115
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T223	8		T169	6		T294	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T224	10		T280	18		T291	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	11		T118	19		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	9		T118	15		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	13		T31	2		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T118	6		T141	2		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	13		T45	10		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	3		T14	2		T226	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	13		T164	10		T167	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T8	2		T12	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	3		T83	2		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T141	6		T146	6		T50	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T143	11		T228	15		T241	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	3		T240	10		T167	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T78	8		T239	10		T231	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T143	12		T39	1		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	2		T221	3		T258	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T16	2		T165	16		T228	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	5		T239	10		T152	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1381	1			T7	11		T11	22		T141	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24