Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25790

1

T1

1

T2

2

T3

142

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22209

1

T1

1

T3

142

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3581

1

T2

2

T5

28

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19440

1

T2

2

T3

139

T4

20

auto[1]

6350

1

T1

1

T3

3

T5

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21690

1

T1

1

T2

2

T3

142

auto[1]

4100

1

T6

7

T7

13

T12

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	410	1			T3	3		T6	10		T12	5
values[0]	64	1			T297	35		T298	3		T299	1
values[1]	828	1			T10	1		T31	12		T118	32
values[2]	3069	1			T2	1		T11	24		T36	22
values[3]	635	1			T5	14		T7	23		T10	1
values[4]	525	1			T1	1		T14	5		T142	1
values[5]	718	1			T2	1		T6	14		T14	1
values[6]	750	1			T5	2		T10	1		T12	11
values[7]	754	1			T7	16		T118	29		T143	29
values[8]	602	1			T8	14		T27	1		T31	5
values[9]	1203	1			T5	12		T6	1		T8	3
minimum	16232	1			T3	139		T4	20		T6	105

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1062	1			T10	1		T31	12		T118	44
values[1]	2897	1			T2	1		T11	24		T12	8
values[2]	837	1			T5	14		T7	23		T44	21
values[3]	543	1			T1	1		T2	1		T6	14
values[4]	664	1			T25	14		T27	1		T142	26
values[5]	695	1			T5	2		T7	16		T10	1
values[6]	725	1			T31	5		T118	29		T143	29
values[7]	704	1			T5	12		T8	14		T27	1
values[8]	844	1			T6	1		T8	3		T14	2
values[9]	183	1			T142	21		T50	1		T150	10
minimum	16636	1			T3	142		T4	20		T6	115

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

4165

1

T5

25

T6

5

T7

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T31	1		T118	7		T141	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	1		T118	16		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T11	24		T36	2		T87	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T12	5		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	12		T44	10		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	14		T44	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	1		T144	1		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	1		T6	7		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T25	1		T142	13		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	1		T27	1		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T37	3		T221	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	2		T7	14		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	3		T143	13		T279	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T118	20		T155	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	14		T220	1		T226	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	12		T27	1		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T27	1		T146	7		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	1		T8	3		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T142	11		T99	16		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T50	1		T150	1		T15	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16468	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T300	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T31	11		T118	5		T149	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T118	16		T37	3		T220	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T36	20		T87	13		T188	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	3		T25	14		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	11		T44	9		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	1		T151	10		T34	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T144	12		T225	2		T219	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	7		T14	2		T164	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	12		T142	13		T290	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T175	4		T40	1		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	2		T221	4		T101	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	2		T12	4		T151	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	2		T143	16		T228	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T118	9		T166	1		T154	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T220	12		T226	12		T166	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T143	13		T41	3		T165	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	11		T164	10		T301	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T221	3		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T142	10		T271	8		T302	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T150	9		T15	3		T253	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	2		T44	1		T45	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T3	3		T6	10		T12	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T114	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T297	4		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T297	14		T298	2		T303	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T31	1		T145	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T118	16		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T11	24		T36	2		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T44	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	12		T144	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	14		T10	1		T12	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T142	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	3		T192	1		T164	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T25	1		T45	11		T142	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T6	7		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	1		T37	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	2		T12	7		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T143	13		T221	5		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	14		T118	20		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	14		T31	3		T146	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T27	1		T141	3		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T27	1		T142	11		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T5	12		T6	1		T8	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16086	1			T3	139		T4	20		T6	105
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T304	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T297	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T297	13		T298	1		T305	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	11		T145	10		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	16		T220	11		T100	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T36	20		T44	9		T87	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	1		T25	14		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	11		T144	12		T191	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	3		T151	10		T15	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T39	2		T224	11		T219	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	2		T164	10		T306	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	12		T142	13		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	7		T175	4		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	2		T101	13		T290	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	4		T40	1		T151	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	16		T221	4		T228	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	2		T118	9		T166	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T31	2		T220	12		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T143	13		T41	3		T166	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T142	10		T149	11		T164	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T14	1		T150	9		T221	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T44	1		T45	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T31	12		T118	6		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T10	1		T118	17		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T11	2		T36	22		T87	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T12	5		T25	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	12		T44	10		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T44	2		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T144	13		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T6	9		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	13		T142	14		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	1		T27	1		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	1		T37	5		T221	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T7	3		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T31	3		T143	17		T279	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T118	10		T155	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T220	13		T226	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T27	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	1		T146	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T8	1		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T142	11		T99	1		T271	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T50	1		T150	10		T15	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16628	1			T3	142		T4	20		T6	115
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T118	6		T141	6		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T118	15		T37	2		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T11	22		T260	11		T177	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	3		T141	12		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	11		T44	9		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	13		T239	10		T223	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T45	10		T219	16		T167	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	5		T14	2		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T142	12		T39	12		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	3		T170	14		T275	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T221	4		T166	5		T307	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T7	13		T12	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	2		T143	12		T83	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T118	19		T113	11		T97	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	13		T226	14		T166	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	11		T141	2		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T146	6		T164	10		T78	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	2		T221	3		T225	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T142	10		T99	15		T271	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T15	3		T308	7		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T300	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T3	3		T6	10		T12	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T114	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T297	5		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T297	14		T298	2		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T31	12		T145	11		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T118	17		T220	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T11	2		T36	22		T44	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	1		T44	2		T25	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	12		T144	13		T191	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T10	1		T12	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	1		T142	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	3		T192	1		T164	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T25	13		T45	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	1		T6	9		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	1		T37	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T12	7		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T143	17		T221	5		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	3		T118	10		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	1		T31	3		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T27	1		T141	1		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T27	1		T142	11		T149	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T5	1		T6	1		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16232	1			T3	139		T4	20		T6	105
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T304	8		T310	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T297	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T297	13		T298	1		T303	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	1		T83	2		T264	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	15		T240	10		T228	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T11	22		T44	9		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	2		T141	12		T50	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	11		T164	12		T226	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	13		T12	3		T15	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T224	11		T219	16		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	2		T164	9		T239	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	10		T142	12		T166	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	5		T243	7		T247	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T39	12		T307	13		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T12	4		T40	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T143	12		T221	4		T83	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	13		T118	19		T113	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	13		T31	2		T146	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T141	2		T143	11		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T142	10		T164	10		T78	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T5	11		T8	2		T221	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21625

1

T1

1

T2

2

T3

142

auto[1]

auto[0]

4165

1

T5

25

T6

5

T7

24